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New entries since:Thu Jan 1 01:00:00 1970
Entry  Thu Sep 16 19:04:06 2021, Patrick Moriishi Freeman, drs_exam_multi with non-v4 boards, default configuration 
    Reply  Sat Sep 18 15:48:30 2021, Stefan Ritt, drs_exam_multi with non-v4 boards, default configuration 
Entry  Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading  
    Reply  Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading  
Entry  Wed Jul 14 14:55:09 2021, Mehrpad Monajem, C code to read the 4 channel with external trigger 
    Reply  Mon Aug 9 12:50:31 2021, Stefan Ritt, C code to read the 4 channel with external trigger 
       Reply  Tue Aug 10 13:57:09 2021, Mehrpad Monajem, C code to read the 4 channel with external trigger 
Entry  Tue May 4 21:18:28 2021, Abaz Kryemadhi, recording only timestamp and amplitude and/or filesize maximum 
    Reply  Wed May 5 10:12:44 2021, Stefan Ritt, recording only timestamp and amplitude and/or filesize maximum 
Entry  Wed Apr 7 03:29:39 2021, Sean Quinn, Unexpected noise in muxout: t_samp related? transp_example.PNGtransp_readout_example_noise.PNGdrs_datasheet_fig11.PNGr0_r1_delay.png
    Reply  Wed Apr 7 08:26:12 2021, Stefan Ritt, Unexpected noise in muxout: t_samp related? 
       Reply  Fri Apr 9 20:22:13 2021, Sean Quinn, Unexpected noise in muxout: t_samp related? ex_cal_wave.png
          Reply  Fri Apr 9 20:55:28 2021, Stefan Ritt, Unexpected noise in muxout: t_samp related? 
             Reply  Fri Apr 9 21:56:54 2021, Sean Quinn, Unexpected noise in muxout: t_samp related? 
Entry  Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings? spikes_16MHz.pngspike_period.pngbetter_spikes_15MHz.pngspike_period_15MHz.png
    Reply  Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings? 
Entry  Fri Feb 26 17:05:26 2021, Tom Schneider, Trouble getting PLL to lock 
    Reply  Fri Feb 26 17:59:14 2021, Stefan Ritt, Trouble getting PLL to lock 
       Reply  Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock 
          Reply  Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock 
             Reply  Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock 
                Reply  Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock 
                   Reply  Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock 
                      Reply  Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock 
                         Reply  Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock 
Entry  Thu Feb 25 17:56:39 2021, Matthias Plum, DRS spike removal for multiple waveforms 
    Reply  Fri Feb 26 08:52:50 2021, Stefan Ritt, DRS spike removal for multiple waveforms 
Entry  Wed Jan 20 12:14:49 2021, Taegyu Lee, drs4 persistence 
    Reply  Wed Jan 20 17:37:51 2021, Stefan Ritt, drs4 persistence 
Entry  Thu Dec 17 09:29:43 2020, Alex Myczko, drs sources on github? 
    Reply  Thu Dec 17 11:31:34 2020, Stefan Ritt, drs sources on github? 
Entry  Wed Oct 21 15:03:13 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register drs4_srin_srout_srclk.pdf
    Reply  Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register Screenshot_2020-10-27_at_13.45.39_.png
       Reply  Tue Oct 27 15:02:09 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
          Reply  Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
             Reply  Wed Oct 28 04:32:19 2020, Seiya Nozaki, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
Entry  Tue Sep 22 17:45:26 2020, Elmer Grundeman, External triggering 
    Reply  Wed Oct 7 10:56:03 2020, Stefan Ritt, External triggering 
       Reply  Wed Oct 7 11:17:52 2020, Elmer Grundeman, External triggering 
Entry  Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading 
    Reply  Mon Aug 31 17:17:30 2020, Stefan Ritt, Channel Cascading Screenshot_2020-08-31_at_16.52.28_.png
Entry  Sat Aug 29 22:00:30 2020, Hans Steiger, Dynamic Range Evaluation Board and Software 
    Reply  Mon Aug 31 10:52:42 2020, Stefan Ritt, Dynamic Range Evaluation Board and Software 
Entry  Wed Feb 20 08:03:04 2019, Lev Pavlov, meg? 
    Reply  Wed Feb 20 08:08:42 2019, Stefan Ritt, meg? 
       Reply  Wed Feb 20 12:13:44 2019, Lev Pavlov, meg? 
          Reply  Wed Feb 20 12:56:56 2019, Stefan Ritt, meg? 
             Reply  Thu Feb 21 09:51:24 2019, Lev Pavlov, no board found 
                Reply  Thu Feb 21 09:57:53 2019, Stefan Ritt, no board found 
                   Reply  Mon Feb 25 08:40:44 2019, Lev Pavlov, no board found 
                      Reply  Mon Feb 25 08:48:27 2019, Stefan Ritt, no board found 
                         Reply  Tue Jul 28 22:40:44 2020, Razvan Stefan Gornea, no board found DRS4_scope.png
Entry  Tue May 26 11:10:27 2020, xggg, Domino wave 
    Reply  Tue May 26 12:44:16 2020, Stefan Ritt, Domino wave Screenshot_2020-05-26_at_12.43.40_.png
Entry  Thu May 21 07:18:48 2020, Keita Mizukoshi, DRS4 Evaluation board control tool 'drscl' with macro file 
    Reply  Fri May 22 12:53:33 2020, Stefan Ritt, DRS4 Evaluation board control tool 'drscl' with macro file 
       Reply  Mon May 25 03:36:12 2020, Keita Mizukoshi, DRS4 Evaluation board control tool 'drscl' with macro file 
Entry  Thu May 21 07:38:05 2020, Keita Mizukoshi, Type check at DOFrame.h in official software 
    Reply  Fri May 22 13:24:51 2020, Stefan Ritt, Type check at DOFrame.h in official software 
Entry  Mon Mar 23 15:03:28 2020, Ajay Krishnamurthy, USB trigger issue 
Entry  Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0? Screenshot.png
    Reply  Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0? 
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