| ID |
Date |
Author |
Subject |
Text |
 |
|
39
|
Sun Feb 21 00:46:01 2010 |
Hao Huan | PLLLCK signal of DRS4 |
|
|
|
42
|
Sun Feb 21 20:27:46 2010 |
Hao Huan | PLLLCK signal of DRS4 |
|
|
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44
|
Mon Feb 22 17:23:59 2010 |
Hao Huan | PLLLCK signal of DRS4 |
|
|
|
46
|
Wed Mar 3 17:36:31 2010 |
Hao Huan | Initialization of the Domino Circuit | Hi Stefan,
I read in the
datasheet that every time after power up |
|
|
48
|
Thu Mar 4 19:14:10 2010 |
Hao Huan | Readout of DRS Data | Hi Stefan,
thanks to your
help I can now successfully keep the Domino |
|
|
49
|
Fri Mar 5 23:29:04 2010 |
Hao Huan | Readout of DRS Data |
|
|
|
50
|
Tue Mar 9 23:28:45 2010 |
Hao Huan | Serial Interface Frequency of the DRS Chip | Hi Stefan,
in the DRS4 datasheet
I read that the optimal frequency for SRCLK |
|
|
53
|
Thu Mar 11 21:37:32 2010 |
Hao Huan | Input Bandwidth of the DRS Chip | Hi Stefan,
I read in the
DRS datasheet that the input bandwidth if |
|
|
55
|
Thu Mar 18 21:38:10 2010 |
Hao Huan | Serial Interface Frequency of the DRS Chip |
|
|
|
57
|
Sun Mar 21 02:03:44 2010 |
Hao Huan | PLL Loop Filter Configuration | Hi Stefan,
in the datasheet
it says at 6GSPS the typical loop filter |
|
|
59
|
Tue Mar 30 22:57:34 2010 |
Hao Huan | ROFS Configuration | Hi Stefan,
according to the
DRS4 datasheet, if we want an input range |
|
|
62
|
Fri Apr 9 17:14:45 2010 |
Hao Huan | Baseline Variation In Data | Hi Stefan,
when I sample
a constant input with the DRS 4 chip, there |
|
|
80
|
Thu May 13 19:14:27 2010 |
Hao Huan | DVDD Problem of DRS 4 | Hi Stefan,
on our board some
DRS chips draw a lot of current through DVDD |
|
|
82
|
Tue May 18 01:47:59 2010 |
Hao Huan | DVDD Problem of DRS 4 |
|
|
|
85
|
Wed May 19 02:24:12 2010 |
Hao Huan | DVDD Problem of DRS 4 |
|
|
|
87
|
Wed May 26 19:18:09 2010 |
Hao Huan | High Frequency Input for DRS | Hi Stefan,
I read in the
DRS datasheet that the bandwidth for the |
|
|
134
|
Sun Oct 23 23:32:28 2011 |
Hao Huan | Phase Shift for ADC Readout | Dear Dr. Ritt,
In the DRS 4 datasheet
it is recommended to sample the analog output |
|
|
140
|
Wed Dec 14 00:44:37 2011 |
Hao Huan | Synchronization Delay in the Firmware for 8051 Controller | Hi Stefan,
I have a question
regarding the DRS 4 evaluation board firmware |
|
|
60
|
Mon Apr 5 17:50:39 2010 |
Heejong Kim | version 1.2 evaluation board with firmware 13279? |
Hi, Stefan,
I found that my collaborator
bought 2 older version of evaluation board
before.
They are the version 1.2 in plastics |
|
|
61
|
Mon Apr 5 17:57:41 2010 |
Heejong Kim | Simple example application to read a DRS evaluation board |
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