Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best,
The sampling points are NOT equidestant, they have varying bin widths of 150ps to 250ps at 5GS/s. That's due the way the DRS4 chip works. You might have neglected that fact in the past, but that would have led to poor timing resolutions (typically 1-2ns resolution only). To get bins with the same width, you have to treat your waveform as a real X/Y points (or better U/T), and the re-sample that cure, maybe spline-interpolated, at 200ps bins.
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g. a sampling point all 200ps for 5GS/s).
How can i fix this?
Can someone provide me the software for the board which is old enough to not have this problem. All my Root interpreters produce problems with this new data format. Which version would be old enough?
All the best and thanks a lot,
According to the datasheet DRS_rev09, the write signal is always 16 cells wide. So when the domino wave runs in infinite mode and be stopped by setting DENABLE low , there are always 16 cells capicitors tracking the input signal . It means that the effective sample cells is 1024-16=1008? That's confusing.
Look at the attached picture. For simplicity, only 4 cells are open and tracking the input signal. Time is flowing from top to bottom. So initially, a train of 4 cells is open. When it's stopped, the train stops not immediately, but kind of "runs against a wall" at the stop cell. So each cell is open for four time ticks effectively, and you can use all 1024 cells.
I am trying to get a DRS4 board to run on Windows 10. I am having problems with the driver installation. I am getting the follwoing message
"There is no driver selected for the device information set or element"
I had specified the path to look for the driver as C:\ProgramFilesx86\DRS\driver\. I also tried the option to look online for the driver. None works. Can anyone help?
You need to disable driver signature enforcement. Then try again with path option.
It helped me.
the drs4 start to generate Dtap signal after reset and standard configuration.
while in reset Denable and Dwrite are low
after reset we put Denable in high
the Dtap starts to toggle, and the plllck stabilizes on about 1V.
After 40Msec the Dtap stops to toggle and the plllck go to 2.5V
Why do the Domino stop working?
No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?
my refclk is 1.25Mhz
what are the inputs and voltage you need to see?
Avdd and Dvdd are 2.5v
Denable is "1" Dwrite "0"
currently i am doing an external reset cycle, after that i am doing the configuration cycle.
should i relay on the internal reset?
the Dtap is toggling for 33.8msec and then just stops.
I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.
Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem on your side.
We have some meesurs to show (attached)
From the screen shots it can be seen that ref+ is not synchronized with Dtap (PLL not working correctly)
And Dspeed is going done to zero after some time.
In our system Dspeed is shorted to pllout.
So it looks like pllout do not pump the RC filter capacitors.
We tested various value of R and C's.
Also we checked that pllout is sorted to Dspeed.
We have some measures to show (attached)
From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)
Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins. So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually helps. Or remove the chip completely and try with another chip. In theory there is the possibility that the internal bond wire of the REFCLK signal has a bad connection, but we tested all chips we send out so we should have seen that. But trying with another chip cannot hurt in general. Next month I'm coming to the Weizman Institute for the ISOTDAQ shool. If you want we can meet there if you don't mind the 120 km drive from Haifa.
Thanks for your input.
We are in the process of assemble another PCB board.
so soon we can compere between two boards.
As for the PLLEN bit, we set it.
We checked several times the soldering of the DRS4 using a microscope.
Everything looks ok.
In what method do you recommend to solder the DRS4?
Thanks for the invitation to meet.
120Km is not so far J
We have resolve the problem, the Dtap is now working correctly.
There were two problems:
We are now setting the address bits to all zero. Failure
to do so result in Dtap stop toggling after several hundred milliseconds.
And not to 1.
Is this a known bug in the chip?
Only bay setting DMODE to zero we got the Dtap to work correctly.
The PLL locks after 1 milisec.
If we set it to one we get Dtap that stop toggling after several hundred milliseconds.
We have test it on two boards, they both worked in the same.
Never did we get a One shot Dtap.
Did you published a errata page to the drs4?
While I can understand 1., I'm puzzeled by 2.
If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This is clearly stated in the data sheet.
Concerning the DMODE bit, we operate all (!) our chips with DMODE=1. Actually this is the default value. After a reset, all register bits are "1", which enables the PLL and causes DTAP to oscillate. If DMODE=1, the DTAP signal should toggle only once (!) since the domino loop is not closed. So the scope traces you showed previously are consistent with the standby mode, but not possible with ANY setting of DMODE.
surrey i forgot to update..
after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111
after making shore that a0-a3 never get 1111 value thae drs4 woks as expected.
The dtap toggols ok.
We can sample and read all the data channels.
So, putting A0-A3 value of 1111 even for very short period " confuse " the DRS and then it start to behave in a strange manner.
Thanks for the update, I will add a note into the data sheet.
Dear Evaluation Board Team,
currently I am facing the problem of digitizing pulses with an amplitude of -0.6V to -0.8V. As the dynamic range of the board is 1Vpp, this should be feasible. However, I do not know how to set in the software a correct range. I see only -0.5V/0.5V, and the two positive options. Normally I would use -0.5V/0.5V and give the thing an offset of 0.4V or so? Is this possible? Where can I set such a offset?
You cannot go below -0.5V for the inputs, since the board does not have an internal negative power supply, which would be necessary for that. If you have -0.8V pulses, the easiest is to use a passive inverter at the input to convert it to a 0.8V pulse.