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  590   Tue Mar 28 21:53:12 2017 Jim Freemandrscl doesn't find eval board but drsosc does (Windows 7)I cannot find the EVAL board using drscl
version 5.06 while the drsosc works fine.
I tried 2 different eval boards and 2 different
  
  15   Fri Oct 16 09:51:03 2009 Jinhong WangDSR4 Full Readout ModeHello Mr. Stefan Ritt
         
In DSR4 DATASHEET Rev.0.8 Page13, I noticed
  
  17   Mon Oct 19 09:06:43 2009 Jinhong WangBIAS Pin of DRS4Dear Mr. Stefan Ritt.
        
Thank u for your timely response on "DSR4
  
  19   Mon Oct 19 11:26:29 2009 Jinhong Wangoutput common mode voltage of DRS4Hello Mr.
Stifan.Ritt
       In
the DSR4 datasheet, it is mentioned that
  
  21   Fri Oct 30 03:31:54 2009 Jinhong Wangoutline dimension of DRS4   QFN_package.jpg 
  23   Mon Dec 14 10:14:16 2009 Jinhong WangTrigger of DRS4Dear Mr. S. Ritt
     The
following is my confusion about the
  
  25   Mon Dec 21 10:17:05 2009 Jinhong WangTrigger of DRS4
  
  27   Tue Dec 22 01:30:55 2009 Jinhong WangTrigger of DRS4
  
  78   Wed May 12 11:47:39 2010 Jinhong WangDRS4 chip model
  
  91   Fri Jun 18 11:31:20 2010 Jinhong WangDVDD Problem of DRS 4

    

       
            
  
  93   Sat Jun 19 10:09:18 2010 Jinhong WangDVDD Problem of DRS 4

    

       
            
  
  94   Tue Jun 22 10:50:19 2010 Jinhong WangReset of DRS4 Hi Stefan, 
      I found
DRS draw a lot of current when applied Reset
  
  96   Tue Jun 22 11:29:26 2010 Jinhong WangReset of DRS4

    

       
            
  
  98   Tue Jun 22 11:37:42 2010 Jinhong WangReset of DRS4

    

       
            
  
  104   Mon Jul 19 12:07:04 2010 Jinhong WangFixed Patter Timing Jitter Hi Stefan, can you give some suggestions
on determination of fixed pattern timing
jitter of DRS4?  Thanks~
  
  106   Wed Jul 21 10:46:32 2010 Jinhong Wang ENOB of DRS Hi, Stefan, I see in your ppt "Design
and performance of 6 GSPS waveform digitizing
chip DRS4" , you define DRS4 ENOB as
  
  110   Tue Oct 12 03:53:37 2010 Jinhong WangReference design for DRS4 active input buffer

    

       
            
  
  121   Mon Jul 4 05:06:00 2011 Jinhong WangFixed Patter Timing Jitter

    

       
            
 hist_stoppos.jpg 
  123   Tue Jul 12 09:49:08 2011 Jinhong WangFixed Patter Timing Jitter

    

       
            
 131MHz.jpg 
  212   Thu Dec 27 00:12:12 2012 Jinhong Wangvariation of sampling capacitorsHi Stefan,
A quick question, what is the typical
variation of the sampling capacitors in DRS4?
  
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