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+    Wed May 9 09:03:52 2018, Stefan Ritt, Manual Rev5.1 Figure 1, optional components     +    Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED     +    Fri Jun 8 08:11:05 2018, Stefan Ritt,      +    Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage     +    Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed     +    Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width     +    Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing     +    Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support     +    Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed     +    Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed     +    Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms     +    Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?     +    Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue     +    Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study     +    Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software     +    Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s)     +    Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points    Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs    Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software    Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit

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