DRS4 Forum

DRS4 Discussion Forum, Page 13 of 45  Not logged in

Find |  Login |  Help

Full | Summary | Threaded | Collapse | Expand     889 Entries

Goto page Previous  1, 2, 3 ... 12, 13, 14 ... 43, 44, 45   Next

Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4    Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4        Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4        Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4        Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model        Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4        Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4    Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4        Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4        Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4    Mon Jul 19 12:07:04 2010, Jinhong Wang, Fixed Patter Timing Jitter    Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS        Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer        Mon Jul 4 05:06:00 2011, Jinhong Wang, Fixed Patter Timing Jitter        Tue Jul 12 09:49:08 2011, Jinhong Wang, Fixed Patter Timing Jitter    Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors        Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors        Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors    Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0?    Wed Oct 25 19:44:25 2023, John Westmoreland, WaveDREAM Design

Goto page Previous  1, 2, 3 ... 12, 13, 14 ... 43, 44, 45   Next

ELOG V3.1.5-fe60aaf