 Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing
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Using a test pulse split into two channels of the DRS4 Evaluation Board v5, I looked at the time resolution using a leading edge threshold.
The voltage and timing calibration was performed. One method (1) is to linearly interpolate between two points of the raw waveform that
is above and below the threshold (this is exactly the algorithm given in read_binary.c in the drs4 source distribution); and another (2) is to |
 Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing
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Just a follow-up update.
It turns out that I was using a cubic spline interpolation with smoothing. If I required the cubic spline to go through the sampled points, then
I obtained similar time resolution as the simple linear interpolation. |
Tue Jul 23 22:31:08 2013, alonzi, Evaluation Board Behavior 
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Working with the DRS evaluation board we noticed some funny behavior: See attatchment 1. In about 1% of scope traces we see the first and last bin take
on a value substantially different from the baseline, note the small spikes on the end of the traces. These spikes occur across all channels and either
appear in all channels or in none. Attachment two shows what several thousand scope traces look like. You can clearly see that some of the traces are offset |
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Tue Jul 23 22:35:08 2013, Stefan Ritt, Evaluation Board Behavior
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alonzi wrote:
Working with the DRS evaluation board we noticed some funny behavior: See attatchment 1. In about 1% of scope traces we see the first and |
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Tue Jul 23 22:42:31 2013, alonzi, Evaluation Board Behavior
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Stefan Ritt wrote:
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Thu Jul 25 01:31:29 2013, Andrey Kuznetsov, Evaluation Board Behavior
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alonzi wrote:
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Sat Jul 13 01:00:15 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello,
I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There
seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or |
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Mon Jul 15 17:26:50 2019, Stefan Ritt, Evaluation Board Test Functionality
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Have you set the trigger correctly to the channel with your signal, polarity and level? Do you undersand the difference between normal and auto trigger?
Why don't you post a screendump. Are you ABSOLUTELY SURE that you have a signal on your cable? Have you tried with another oscilloscope? Are you sure
that your SMA connector is good? |
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Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello Stefan,
Thanks for the quick reply. The issue was a faulty SMA connector, should have checked this first. Signal looks good now.
Thanks for your time, |
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Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors
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| Quick question - what type of connectors are used for the trigger and clock in/out on the v4 eval board? |
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Thu Jun 20 01:36:48 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the
readout state machine from the evaluation board firmware. |
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Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state
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Dear Andrew,
the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately
the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline |
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Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
Thanks so much for clarifying this. We made wait_vdd a parameter controlled by software and will try to experiment with it to find some compromise
between deadtime and the offset added by the droop in VDD. |
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Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing
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Hi,
I'm running a LIDAR application that requires that every outgoing pulse be captured. My current setup firess sets of 20-50 pulses at
1 ms intervals, about 10 times a second, but only 10-20 pulses a second are captured. |
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Mon Oct 2 16:08:05 2017, Stefan Ritt, Event acquisition pace for irregular timing
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As written in the documentation, the DRS evaluaiton board has a maximum trigger capability of ~500 Hz. This is limited by the USB bus which has a finite
data transfer rate. If you build your own electronics around the chip (like many other groups are doing), you can squeeze this to a few kHz, but it is
some development effort. |
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Wed Jan 14 12:02:04 2009, Stefan Ritt, External Trigger Input requirements
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Several people mentioned that the external trigger input (TTL) does not work on the DRS4 Evaluation Board Rev. 1.1. This is not true. The requirement
however is that the input signal must exceed approximately 1.8V. Since the input is terminated with 50 Ohms, not all TTL drivers may deliver enough current
to exceed this threshold. To verify this, the trigger signal can be monitored with an oscilloscope at test point J24. Only if the input signal exceeds |
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Wed Jan 14 13:41:44 2009, Stefan Ritt, External Trigger Input requirements
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Another tricky issue comes from the fact that the external TTL trigger and the comparator are in a logical OR. So if the comparator level is set
such that the signal is always over the threshold, the trigger is always "on" and the TTL trigger does not have any effect. It is therefore necessary |
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Tue Oct 26 10:41:46 2021, Mehrpad Monajem, External trigger and drs_exam
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Hi Stefan,
I have two problems regarding using the drs_exam file with external trigger: |
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Tue Oct 26 12:00:51 2021, Stefan Ritt, External trigger and drs_exam
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1. Why should your waveform start from 0 to 5ns? I don't get your point. Whenever you trigger a readout, you get a 200ns wide time window, and by
definition it starts at zero.
2. In the software distribution you have a drs_exam_2048.cpp program. Note that your board needs to be physically modified before delivery to |
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Tue Oct 26 15:05:18 2021, Mehrpad Monajem, External trigger and drs_exam
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Thanks for your reply.
1- I want to have a window size of 25.6ns instead of 200ns at 5GSPS. I have a 200khz high voltage pulser, which applies a pulse to my sample.
I want to digitize the detector signal for each pulse (each pulse has a 25.6ns period). The pulser and digitizer use same 200khz trigger signal from each |