 Sun May 26 13:08:52 2013, tmiron alon,
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Hallo,
I'm using DRS4 Evaluation Board Rev 4.0 and I'm trying to change the output of the samples to be an average of # measurements (1000
or even more) |
 Fri Jun 7 10:22:48 2013, Stefan Ritt,
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tmiron alon wrote:
Hallo, |
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Tue Aug 27 16:14:49 2013, lengchongyang,
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Hello everyone！I'm a new user of DRS4 board,but it seems that some files are missing
in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!
T |
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Wed Aug 28 04:05:48 2013, lengchongyang,
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lengchongyang wrote:
Hello everyone！I'm a new user of DRS4 |
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Wed Nov 6 16:35:42 2013, Stefan Ritt,
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lengchongyang wrote:
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Fri Mar 11 19:50:18 2016, Dominik Neise,
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Hello Stefan,
I just stumbled again over a phrase in the DRS4 datasheet I never really understood, but didn't find the time to ask.
On page 8 it says: "An internal circuit ensures that the write signal is always 16 cells wide." |
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Tue Mar 22 12:54:41 2016, Stefan Ritt,
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Yes this is correct. But it is a sample-and-hold circuit. So the sampling cell follows the input for 3.2 ns, then samples and holds the current value
at the end of the period.
Dominik |
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Thu Oct 6 15:23:18 2016, Will Flanagan,
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Hi Stefan,
That is exactly what I'm looking for. Thanks again!
Will |
Thu Jun 7 16:27:21 2018, Phan Van Chuan, 
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Dear Stefan,
I am using an DRS4 board to test the signal from an scintillator detector; It has connected well to the computer on DRS Oscilloscope (Figure
1). Now, I am having a problem of developing from the code of the drs_exam program, because the DRS4 board has not connected to the computer when translation |
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Fri Jun 8 08:11:05 2018, Stefan Ritt,
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Several people reported this problem, but we cannot reproduce it at our lab. Both the oscilloscope and the command line interface use exactly the same
code to connect to the board. Have you tried the solution reported here: elog:657 ?
Best, |
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Tue Apr 12 10:40:36 2022, LynseyShun,
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Hello, I am Lynsey. now I set A3-A0 to 1001 in ROI mode, but only OUT0 has output, and the other seven channels(OUT1-OUT7) do not output corresponding
waveforms.
In ROI mode, can OUT0-OUT7 output sampled waveforms at the same time? |
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Tue Apr 12 10:49:27 2022, Stefan Ritt,
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A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works in our designs. Maybe double check the address lines with an oscilloscope.
Stefan
LynseyShun |
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Thu Jun 16 05:31:25 2022, LynseyShun,
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Thank you very much for your help!
Stefan
Ritt wrote:
A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works |
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Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource
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Hi
I have a question about the function SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp)
In the implementation there is the following comment: |
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Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource
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Your first assumption is correct, e.g.
source = 00000000'00000001 = 0x0001 ==> CH1
source = 00010001'00000000 = 0x1100 ==> CH1 and EXT |
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Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS
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Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS)
= 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained
from DC offset Correction, hence 11.5 bit is for DC input, am i right? If true, what about ENOB for AC input in the whole analog bandwidth? thanks~ |
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Wed Jul 21 10:58:20 2010, Stefan Ritt, ENOB of DRS
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Jinhong Wang wrote:
Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip |
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Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
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Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
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Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
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Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |