DRS4 Forum
  DRS4 Discussion Forum, Page 2 of 15  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
Entry  Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4 
Hi Stefan,
    in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However
    Reply  Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 start_1ghz.png


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
       Reply  Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
          Reply  Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4 


    
        
            Hao Huan wrote:
        
        
            
            
             Reply  Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
                Reply  Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4 


    
        
            Hao Huan wrote:
        
        
            
            By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN
                   Reply  Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
                      Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 


    
        
            Hao Huan wrote:
        
        
            
            
            
Entry  Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit 
Hi Stefan,
    I read in the datasheet that every time after power up the Domino wave in DRS4 needs to be started and stopped once to initialize
the Domino circuit. However in your firmware it seems the chip immediately goes into the idle state after reset. Is that Domino circuit initialization
    Reply  Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
Entry  Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data 
Hi Stefan,
    thanks to your help I can now successfully keep the Domino wave running at a stable frequency and maintain the channel cascading
information in the Write Shift Register. (Since you told me WSR always reads and writes at the same time, I think I need to rewrite the information back
    Reply  Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
    Reply  Thu Mar 11 11:45:52 2010, Stefan Ritt, Readout of DRS Data 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
Entry  Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip 
Hi Stefan,
    I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth in the transparent
mode is 50MHz. Since in the transparent mode the input is routed to the output, does it mean the input bandwidth also gets reduced in the transparent mode?
    Reply  Fri Mar 12 08:04:44 2010, Stefan Ritt, Input Bandwidth of the DRS Chip 


    
        
            Hao Huan wrote:
        
        
            
            I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth
Entry  Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
Hi Stefan,
    in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is
toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz?
    Reply  Wed Mar 10 10:07:28 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip 


    
        
            Hao Huan wrote:
        
        
            
            in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation
       Reply  Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
          Reply  Thu Mar 18 22:10:41 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip 


    
        
            Hao Huan wrote:
        
        
            
             
Entry  Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration 
Hi Stefan,
    in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. If I want to run the Domino
wave nominally at 1GHz, i.e. with a reference clock frequency around 0.5MHz, is there any recommended loop filter configuration? Is the setup of the evaluation
    Reply  Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration 


    
        
            Hao Huan wrote:
        
        
            
            in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF.
Entry  Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter 
Hi all

    Reply  Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter 


    
        
            lorenzo neri wrote:
        
        
            
            Hi all
Entry  Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data 
Hi Stefan,
    when I sample a constant input with the DRS 4 chip, there was a baseline variation showing up as a saw-tooth pattern which grows
with the absolute value of the differential input. Do you think this is the kind of baseline variation mentioned in the evaluation board manual, i.e. coming
    Reply  Tue Apr 13 13:56:07 2010, Stefan Ritt, Baseline Variation In Data 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
Entry  Tue Apr 28 11:44:07 2009, Stefan Ritt, Simple example application to read a DRS evaluation board drs_exam.cpp
Several people asked for s simple application to guide them in writing their own application to read out a DRS board. Such an application has been added
in software revions 2.1.1 and is attached to this message. This example program drs_exam.cpp written
in C++ does the following necessary steps to access a DRS board:
    Reply  Wed Apr 29 07:57:33 2009, Stefan Ritt, Simple example application to read a DRS evaluation board DRS.cppDRS.h
 

    
        
            Stefan Ritt wrote:
        
        
            
    Reply  Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board 


    
        
            Stefan Ritt wrote:
        
        
            
            Several people asked for s simple application to guide them in writing their own application to read out
       Reply  Tue Apr 13 14:15:16 2010, Stefan Ritt, Simple example application to read a DRS evaluation board 


    
        
            Heejong Kim wrote:
        
        
            
            
            
Entry  Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279? 

Hi, Stefan,

I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware
13191.

Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.

Thanks,
Heejong

    Reply  Wed Apr 14 16:34:28 2010, Stefan Ritt, version 1.2 evaluation board with firmware 13279? 


    
        
            Heejong Kim wrote:
        
        
            
            
Hi, Stefan,

I found that my collaborator bought 2 older version of evaluation board before.
They
Entry  Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration 
Hi Stefan,
    according to the DRS4 datasheet, if we want an input range centered around U0, the ROFS should be 1.55V-U0. However when I read
the codes of the evaluation board application, ROFS seems to be 1.6V-1.25*U0 where the coefficient 1.25 is said to come from sampling cell charge injection
    Reply  Thu Apr 15 13:48:40 2010, Stefan Ritt, ROFS Configuration 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
Entry  Wed May 5 22:30:50 2010, Ignacio Diéguez Estremera, Random noise spec in datasheet 
Hi,
According to DRS4's datasheet, the random noise is 0.35mVrms. Is this the input equivalent noise voltage? It is computed over the 0-950MHz frequency
band?
    Reply  Thu May 6 08:15:39 2010, Stefan Ritt, Random noise spec in datasheet 


    
        
            Ignacio Diéguez Estremera wrote:
        
        
          
 
            Hi,
Entry  Sun May 2 18:36:14 2010, Ignacio Diéguez Estremera, DRS4 chip model 
Hi all,
i'm an electronics engineering student at UCM (Madrid) working on my master's thesis within the CTA collaboration. I'm designing the readout electronics
for the telescope's camera, and i'm focusing in using GAPDs instead of PMTs and using the domino chip for the sampling of the signal. I was wondering if
    Reply  Mon May 3 11:09:12 2010, Stefan Ritt, DRS4 chip model 


    
        
            Ignacio Diéguez Estremera wrote:
        
        
          
 
            Hi all,
       Reply  Mon May 3 17:06:02 2010, Ignacio Diéguez Estremera, DRS4 chip model 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
          Reply  Mon May 3 17:10:29 2010, Stefan Ritt, DRS4 chip model 


    
        
            Ignacio Diéguez Estremera wrote:
        
        
          
 
            
            
             Reply  Mon May 3 23:21:55 2010, Ignacio Diéguez Estremera, DRS4 chip model 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
                Reply  Tue May 4 11:26:21 2010, Stefan Ritt, DRS4 chip model DRS4_S-Parameter.pdf


    
        
            Ignacio Diéguez Estremera wrote:
        
        
          
 
            So i guess i won't be able to include drs4 in my simulations :-(. Any other
                   Reply  Tue May 4 16:23:16 2010, Ignacio Diéguez Estremera, DRS4 chip model 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
                   Reply  Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model 


    
        
            Stefan Ritt wrote:
        
        
            
      
                      Reply  Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model 


    
        
            Jinhong Wang wrote:
        
        
            
            
            
Entry  Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS 
Hi Stefan,
    I read in the DRS datasheet that the bandwidth for the transparent mode OUT+ is only 200MHz which I think cannot be improved
by any active input buffer; so if you want to operate the chip for really high frequency input, would it be better to feed on-board discriminators not
    Reply  Tue Jun 1 13:36:18 2010, Stefan Ritt, High Frequency Input for DRS 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
Entry  Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4 
Hi Stefan,
    on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our
board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization
    Reply  Fri May 14 08:40:14 2010, Stefan Ritt, DVDD Problem of DRS 4 


    
        
            Hao Huan wrote:
        
        
            
            Hi Stefan,
       Reply  Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
          Reply  Tue May 18 08:23:07 2010, Stefan Ritt, DVDD Problem of DRS 4 


    
        
            Hao Huan wrote:
        
        
            
            
            
             Reply  Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
                Reply  Wed May 19 09:16:02 2010, Stefan Ritt, DVDD Problem of DRS 4 


    
        
            Hao Huan wrote:
        
        
            
            
            
                   Reply  Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
                      Reply  Fri Jun 18 11:45:18 2010, Stefan Ritt, DVDD Problem of DRS 4 


    
        
            Jinhong Wang wrote:
        
        
            
             
                         Reply  Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
Entry  Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4 
 Hi Stefan, 
      I found DRS draw a lot of current when applied Reset after power on,  and the PLL does not work properly. I believe
there was something that I misunderstood. So,  what will happen when Reset is applied more than once after power on? . Though the chip worked well
    Reply  Tue Jun 22 11:02:30 2010, Stefan Ritt, Reset of DRS4 


    
        
            Jinhong Wang wrote:
        
        
            
             Hi Stefan, 
       Reply  Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
          Reply  Tue Jun 22 11:35:18 2010, Stefan Ritt, Reset of DRS4 


    
        
            Jinhong Wang wrote:
        
        
            
            
            
             Reply  Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
Entry  Mon Jul 12 16:07:37 2010, Stefan Ritt, Announcement evaluation board V3 eval3.png
Dear DRS4 users,
a new version of the evaluation board has been designed and is in production now. The main difference is that it uses active input amplifiers,
which result in an analog bandwidth of 700 MHz (as compared with the 220 MHz of the previous board) at moderate power consumption, so the board can still
Entry  Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS 
 Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS)
= 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained
from DC offset Correction, hence 11.5 bit is for DC input, am i right?  If true, what about ENOB for AC input in the whole analog bandwidth?  thanks~
    Reply  Wed Jul 21 10:58:20 2010, Stefan Ritt, ENOB of DRS 


    
        
            Jinhong Wang wrote:
        
        
            
             Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip
Entry  Tue May 18 09:24:02 2010, Stefan Ritt, Reference design for DRS4 active input buffer ac.pngac_bw.pngdc.pngdc_bw.pngDRS4_ft_V3.jpg
The design of high frequency differential input stages with the DRS4 is a challenge, since the chip draws quite some current at the input (up to 1 mA
at 5 GSPS), which must be sourced by the input buffer. A simple transformer as used in the DRS4 Evaluation Board 2.0 limits the bandwidth to 220 MHz. In
meantime two active input stages have been worked out and successfully been tested, both utilizing the THS4508 differential amplifier. The first design
    Reply  Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer 


    
        
            Stefan Ritt wrote:
        
        
            
            The design of high frequency differential input stages with the DRS4 is a challenge, since the chip
       Reply  Tue Nov 16 16:38:06 2010, Stefan Ritt, Reference design for DRS4 active input buffer 


    
        
            Jinhong Wang wrote:
        
        
            
             
Entry  Sat Feb 19 17:25:29 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards 
 Dear sir,
We have two evaluation boards of DRS4. We would like to use 8 inputs to be recorded on a trigger and we would like to find the relative time difference
of inputs. So is it possible to synchronize the sampling frequency of the two evaluation boards. 
    Reply  Sat Feb 19 22:46:35 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards 


    
        
            S S Upadhya wrote:
        
        
            
             Dear sir,
       Reply  Mon Feb 21 08:10:31 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
          Reply  Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
ELOG V3.1.5-fe60aaf