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New entries since:Thu Jan 1 01:00:00 1970
ID Date Author Subject Text Attachments
  820   Wed Apr 7 03:29:39 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Dear DRS4 team,

I'm experiencing some issues
that seem to be isolated to the ASIC, and
 transp_example.PNGtransp_readout_example_noise.PNGdrs_datasheet_fig11.PNGr0_r1_delay.png 
  819   Fri Mar 5 09:39:42 2021 Stefan RittTrouble getting PLL to lockThat probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock
  
  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lockI found the problem, and it had nothing
to do with the CMOS clock input.  As
it turns out, even though I was using the
  
  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lockThats not a simple modification to my PCB,
but I'll give it a try.  Thanks
for your help
  
  816   Fri Feb 26 22:12:58 2021 Stefan RittTrouble getting PLL to lockSounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals
  
  815   Fri Feb 26 21:24:39 2021 Tom SchneiderTrouble getting PLL to lockProbe capacitance makes that tricky - if
I put my probe on DSPEED, I see that it starts
at approx. 2.5V then gradually decreases
  
  814   Fri Feb 26 20:32:25 2021 Stefan RittTrouble getting PLL to lockCan you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?

  
  813   Fri Feb 26 18:33:52 2021 Tom SchneiderTrouble getting PLL to lockStefan,

Thanks for responding so quickly. 
Yes I have my clock source going to REFCLK+
  
  812   Fri Feb 26 17:59:14 2021 Stefan RittTrouble getting PLL to lockI guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else!
  
  811   Fri Feb 26 17:05:26 2021 Tom SchneiderTrouble getting PLL to lockHello,

I am working on a custom PCB design
with the DRS4 chip, and I can't get the
  
  810   Fri Feb 26 08:52:50 2021 Stefan RittDRS spike removal for multiple waveformsJust look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid
  
  809   Thu Feb 25 17:56:39 2021 Matthias PlumDRS spike removal for multiple waveformsHi,

Is there a way that someone can
help me and my student to enable RemoveSymmetricSpikes
  
  808   Wed Jan 20 17:37:51 2021 Stefan Rittdrs4 persistenceThe chip itself can only sample a single
waveform, that must be done in the attached
software. The current DRSOscilloscope software
  
  807   Wed Jan 20 12:14:49 2021 Taegyu Leedrs4 persistenceDear all,

I have a question about the function that
drs4 can perform.
  
  806   Thu Dec 17 11:31:34 2020 Stefan Rittdrs sources on github?Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/

But development kind of stalled, so there
  
  805   Thu Dec 17 09:29:43 2020 Alex Myczkodrs sources on github?Are there plans to add the drs software to
github? (asking because I have users @ethz.ch
that want to use it on debian,
  
  804   Wed Oct 28 04:32:19 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Stefan,

OK, it's good to hear! Thank you!
  
  803   Tue Oct 27 15:24:38 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift registerThis is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just
  
  802   Tue Oct 27 15:02:09 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Stefan,

Thank you for your reply.
  
  801   Tue Oct 27 13:37:23 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Seiya,

1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure
 Screenshot_2020-10-27_at_13.45.39_.png 
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