| ID |
Date |
Author |
Subject |
Text |
 |
|
695
|
Wed May 9 14:07:10 2018 |
Alec Shackleford | WIndows Connection problem with drs507 SOLVED | Thank you for this fantastic solution.
I had almost reinstalled windows 7 to see
if that would solve the issue! |
|
|
696
|
Mon May 14 09:21:29 2018 |
Alessio Berti | WIndows Connection problem with drs507 SOLVED | Hi,
I have a machine with Windows 10
and the solution provided by Steven works |
|
|
697
|
Thu May 17 13:29:34 2018 |
Stefan Ritt | "Symmetric spikes" fixed | Good news for all DRS4 users. After many
years, I finally understand where the "symmetric
spikes" come from and how to fix them. |
|
|
698
|
Thu Jun 7 16:27:21 2018 |
Phan Van Chuan | | Dear Stefan,
I am using an DRS4 board to test
the signal from an scintillator detector; |
|
|
699
|
Fri Jun 8 08:11:05 2018 |
Stefan Ritt | | Several people reported this problem, but
we cannot reproduce it at our lab. Both the
oscilloscope and the command line interface |
|
|
700
|
Wed Jun 13 13:23:17 2018 |
Julian Kemp | Maximum analog input voltage | Dear all,
I have been wondering what the
maximum analog input voltage for the DRS4 |
|
|
701
|
Wed Jun 13 13:42:47 2018 |
Stefan Ritt | Maximum analog input voltage | In principle the numbers in the manual
are correct. But they relate to pulses of
a certain length, because the input protection |
|
|
702
|
Wed Jun 13 16:34:28 2018 |
Julian Kemp | Maximum analog input voltage | Thank you! That solves my problem.
|
|
|
703
|
Tue Jun 19 06:42:23 2018 |
Phan Van Chuan | The data acquisition speed | Dear Stefan,
We are using an DRS4 board V5.1
for building a metering system for the scintillator |
|
|
704
|
Tue Jun 19 10:05:50 2018 |
Stefan Ritt | The data acquisition speed | How do you tigger the board? In your code
below you start the board (StartDomino())
and then wait for a trigger. Setting the |
|
|
705
|
Tue Jun 19 12:54:51 2018 |
Phan Van Chuan | The data acquisition speed | Thank Stefan Ritt, I added the SoftTrigger()
just after StartDomino(), so now, The data
acquisition speed the same speed as in the |
|
|
706
|
Thu Jun 28 19:55:45 2018 |
Woon-Seng Choong | Negative Bin Width | I am using a DRS4 Evaluation Board v5 and
running the drsosc.exe version 5.06 on
a Window 7 machine. I have performed the |
|
|
707
|
Fri Jun 29 07:51:33 2018 |
Stefan Ritt | Negative Bin Width | Yes that's normal. A negative cell
bin width means that the next cell N+1 samples
the input signal before cell N. This can |
|
|
708
|
Mon Jul 16 19:39:35 2018 |
Woon-Seng Choong | Effect of interpolation on timing | Using a test pulse split into two channels
of the DRS4 Evaluation Board v5, I looked
at the time resolution using a leading edge |
|
|
709
|
Fri Jul 20 00:44:13 2018 |
Woon-Seng Choong | Effect of interpolation on timing | Just a follow-up update.
It turns out that I was using a
cubic spline interpolation with smoothing. |
|
|
710
|
Wed Aug 1 00:49:30 2018 |
Sean Quinn | Optimal readout speed | Dear DRS4 team,
On page 3 of the data sheet, Table
1. for readout speed a typical value of 10 |
|
|
711
|
Mon Aug 13 19:44:59 2018 |
Martin Petriska | Latch delay support | Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, |
|
|
712
|
Tue Aug 14 06:10:49 2018 |
Stefan Ritt | Latch delay support | I put that on the wish list, but I won't
have time for that in the next months.
Stefan |
|
|
713
|
Tue Aug 21 14:36:44 2018 |
Stefan Ritt | Optimal readout speed | The analog output of the DRS4 chip needs
some time to settle. In principle it need
an infinite amout of time (exponential curve) |
|
|
714
|
Mon Sep 3 11:17:26 2018 |
Martin Petriska | "Symmetric spikes" fixed | Hi,
Is it possible to fix it by FPGA
changes? I see readout cycle (proc_drs_reedout) in |
|