| ID |
Date |
Author |
Subject |
Text |
 |
|
707
|
Fri Jun 29 07:51:33 2018 |
Stefan Ritt | Negative Bin Width | Yes that's normal. A negative cell
bin width means that the next cell N+1 samples
the input signal before cell N. This can |
|
|
712
|
Tue Aug 14 06:10:49 2018 |
Stefan Ritt | Latch delay support | I put that on the wish list, but I won't
have time for that in the next months.
Stefan |
|
|
713
|
Tue Aug 21 14:36:44 2018 |
Stefan Ritt | Optimal readout speed | The analog output of the DRS4 chip needs
some time to settle. In principle it need
an infinite amout of time (exponential curve) |
|
|
715
|
Tue Sep 4 13:04:30 2018 |
Stefan Ritt | "Symmetric spikes" fixed | Yes it's possible, but I have to find
time for that. The software of the evaluation
board takes care of the spikes ("remove |
|
|
718
|
Wed Sep 26 14:44:14 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | The "Trigger OUT" has changed
recently. It goes high on a new trigger,
but then STAYS high until the board has been |
|
|
721
|
Wed Sep 26 19:21:03 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | In meantime I even updated the manual.
Stefan
|
|
|
723
|
Thu Nov 8 09:57:26 2018 |
Stefan Ritt | Pi attenuator on eval board inputs? | The attenuator compensates for the gain
of the buffer which is slightly above one.
In addition, it serves as a "placeholder" |
|
|
725
|
Thu Nov 8 11:54:33 2018 |
Stefan Ritt | Timing Issue | That's not a bug, but a feature of the DRS4
chip. The time bins have different values
by the properties of the chip. They are generated |
|
|
729
|
Wed Jan 30 08:02:25 2019 |
Stefan Ritt | DRS4 domino wave stability study | The Domino wave is most stable at 5 GSPS,
slowly degrades down to 3-2 GSPS, and at
1GSPS gets some significant jitter. This |
|
|
730
|
Wed Jan 30 17:08:58 2019 |
Stefan Ritt | ROOT Macro for data acquired with the newest software | This one elog:361
should still work.
Stefan |
|
|
732
|
Sat Feb 2 10:10:22 2019 |
Stefan Ritt | Saving Rate (only 15Acq/s) | The reduction of rate is because you save
in XML format, which is an ASCII format,
so human readable, but takes long to write. |
|
|
734
|
Mon Feb 4 16:46:04 2019 |
Stefan Ritt | Different Distances between the sampling points | The sampling points are NOT equidestant,
they have varying bin widths of 150ps to
250ps at 5GS/s. That's due the way the |
|
|
736
|
Mon Feb 4 18:18:22 2019 |
Stefan Ritt | Different Distances between the sampling points | elog:361
|
|
|
738
|
Wed Feb 20 08:08:42 2019 |
Stefan Ritt | meg? | You have to change the path to libusb-1.0.lib
to the one where you installed it.
Stefan |
|
|
740
|
Wed Feb 20 12:56:56 2019 |
Stefan Ritt | meg? | No idea. Maye some access problem. Have
you tried to start your program under an
admin account? |
|
|
743
|
Thu Feb 21 09:57:53 2019 |
Stefan Ritt | no board found | Could be. Have you tried that elog:657
Stefan
|
|
|
745
|
Mon Feb 25 08:48:27 2019 |
Stefan Ritt | no board found | "dynamic" or "static"
does not matter, as long as you don't
use your program on another computer. I have |
|
|
750
|
Fri Apr 12 09:55:50 2019 |
Stefan Ritt | multi-board | Subtract 16 ns from your measured value
;-)
Stefan |
|
|
752
|
Fri Apr 12 12:50:18 2019 |
Stefan Ritt | multi-board | If you have two signal going through two
cables, the cable have never the same length
(on a scale of picoseconds), and you have |
|
|
754
|
Fri Jun 21 12:54:47 2019 |
Stefan Ritt | Evaluation firmware wait_vdd state | Dear Andrew,
the posting you mention is still
accurate. Any power supply will drop when |
|