Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best,
The sampling points are NOT equidestant, they have varying bin widths of 150ps to 250ps at 5GS/s. That's due the way the DRS4 chip works. You might have neglected that fact in the past, but that would have led to poor timing resolutions (typically 1-2ns resolution only). To get bins with the same width, you have to treat your waveform as a real X/Y points (or better U/T), and the re-sample that cure, maybe spline-interpolated, at 200ps bins.
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g. a sampling point all 200ps for 5GS/s).
How can i fix this?
Can someone provide me the software for the board which is old enough to not have this problem. All my Root interpreters produce problems with this new data format. Which version would be old enough?
All the best and thanks a lot,
Hey. Strange problem. Why does the compiler refer there at all? Library installed drsosc works
LINK : fatal error LNK1104: cannot open file "C:\meg\online\drivers\drs\libusb-1.0\libusb-1.0.lib"
You have to change the path to libusb-1.0.lib to the one where you installed it.
Great, drs_exam compiles without problems. Now when you run the compiled file drs_exam writes board not found, but drsosc and drscl work without problems. What could possibly be the matter?
thanks for your patience
No idea. Maye some access problem. Have you tried to start your program under an admin account?
Hey. Yes, the program is running as administrator. By the way, this is win10. Your drs_exam works fine. My drs_exam compiled wrote no board found. Maybe this is a problem like in the post https://elog.psi.ch/elogs/DRS4+Forum/698. Maybe there were solutions to the problems?
Could be. Have you tried that elog:657
Hello. When compiling drs_exam, do you need to use a "static "version of usblib or a "dynamic" version?"The problem with "no board found" is not solved. Thanks for your help.
"dynamic" or "static" does not matter, as long as you don't use your program on another computer. I have no more idea about the "no board found" problem. It works ok on all computers I tried at our lab.
When connecting the board and running the Zadig program, some Windows PCs may return "driver installation failed." I coudn't find the solution from their download website. So I started the drscl first. Apparently it shows: Successfully scanned, but no boards found. Therefore I checked the Device Manager. A breakdown warning triangle appears under the serial port...
The possible solution may be found here.
Infact, the WinUsb driver has been in existence in your PC. One can just follow the instructions here:
In the wizard, somehow the default setting displays Microsoft Device on the Top of the list and replaced the WinUsb Device. You can easily re-load the WinUsb Device. Just ignore the WARNING from the device manager. The board should work fine now.
The older root macro did not work for me for data acquired with the newest software.
so for the newest software and multiple boards, I modified the read_binary.cpp into read_binary.C for those who like to use the root macro, see the attachment.
I have emailed email@example.com a couple of times regarding the pricing of the evaluation kits for academic use in India and have not received any reply and hence writing in this forum. Could you please help me in this?
Thanks and regards,
Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks
Subtract 16 ns from your measured value ;-)
I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but simultaneously in parallel to all the boards, will this shift go? Thanks
If you have two signal going through two cables, the cable have never the same length (on a scale of picoseconds), and you have to calibrate that anyway. So a proper timing calibration is not a crutch.
What do you mean by "manual 50ps"? The manual does not mention any resolution. In my experience, you can achieve about 10ps between channels of the SAME board easily. The phase shift between boards in multi-mode is always there, unfortunately there are no cable which conduct current faster than the speed of light! What you can do is to split a common reference clock and send a copy to one channel of each board, then calculate the timing relative to the next edge in that reference signal. This way you get rid of the phase shift, but this is also a kind of calibration, so in your laguange that would be "a big crutch".
I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the readout state machine from the evaluation board firmware.
I see in the state machine of the eval board firmware that after a trigger is received, the FPGA goes into the start readout state and then into "wait_vdd", where the FPGA waits "~120 us for vdd to stabilize" before reading out the ADC.
Our application is sensitive to deadtime and this wait_vdd state adds very significantly. I am trying to find anything explaining the necessity of wait_vdd in the documentation / elog and have only found so far your old forum posting, https://elog.psi.ch/elogs/DRS4+Forum/12
Does this forum posting explain wait_vdd or is there a another purpose that I have missed?
If this post is relevant to wait_vdd, does the advice of large capacitance and an LDO with fast transient response still apply or are there any new recommendations?
the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline will also be shifted by about 40 mV. If you are sensitive to dead time, you can remove the wait_vdd state completely, but then you have to deal with varying baseline shifts. If you have narrow signals sitting on a broad baseline, you can correct for this by measuring the baseline outside your signal, then subtracting it before integrating your pulse. If you have lots of pile-up in your signals, it might sometimes be hard to evaluate the baseline on an event-by-event basis.
Thanks so much for clarifying this. We made wait_vdd a parameter controlled by software and will try to experiment with it to find some compromise between deadtime and the offset added by the droop in VDD.