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    Reply  Wed Jun 26 13:08:42 2019, Stefan Ritt, drs_exam is always reading out a sin wave 
    Reply  Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave 
    Reply  Mon Jul 15 17:26:50 2019, Stefan Ritt, Evaluation Board Test Functionality 
    Reply  Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance 
    Reply  Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance 
    Reply  Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register? 
    Reply  Tue Aug 27 09:14:03 2019, Stefan Ritt, DRS4 
    Reply  Mon Oct 14 10:14:46 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
    Reply  Mon Oct 14 12:56:13 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
    Reply  Mon Oct 14 15:27:09 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
    Reply  Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0? 
    Reply  Fri May 22 12:53:33 2020, Stefan Ritt, DRS4 Evaluation board control tool 'drscl' with macro file 
    Reply  Fri May 22 13:24:51 2020, Stefan Ritt, Type check at DOFrame.h in official software 
    Reply  Tue May 26 12:44:16 2020, Stefan Ritt, Domino wave Screenshot_2020-05-26_at_12.43.40_.png
    Reply  Mon Aug 31 10:52:42 2020, Stefan Ritt, Dynamic Range Evaluation Board and Software 
    Reply  Mon Aug 31 17:17:30 2020, Stefan Ritt, Channel Cascading Screenshot_2020-08-31_at_16.52.28_.png
    Reply  Wed Oct 7 10:56:03 2020, Stefan Ritt, External triggering 
    Reply  Tue Oct 27 13:37:23 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register Screenshot_2020-10-27_at_13.45.39_.png
    Reply  Tue Oct 27 15:24:38 2020, Stefan Ritt, Timing diagram of SROUT/SRIN signal to write/read a write shift register 
    Reply  Thu Dec 17 11:31:34 2020, Stefan Ritt, drs sources on github? 
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