 Wed Jan 20 17:37:51 2021, Stefan Ritt, drs4 persistence
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The chip itself can only sample a single waveform, that must be done in the attached software. The current DRSOscilloscope software coming with the evaluation
board has not yet implemented that, but if you write your own software you can do so.
Taegyu |
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Fri Feb 26 08:52:50 2021, Stefan Ritt, DRS spike removal for multiple waveforms
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Just look at the definition of the function below, all parameters are explained there. In meantime we have a firmware fix to avoid the spikes inside
the chip, but I have not yet found time to update the evaluation board.
Stefan |
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Fri Feb 26 17:59:14 2021, Stefan Ritt, Trouble getting PLL to lock
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I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!
There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some
ideas: |
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Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock
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Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?
Tom
Schneider wrote:
Stefan, |
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Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock
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Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB
trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2
is not really working. |
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Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock
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That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros
into the config register, thus disabling the PLL. Shame that I haven't thought of this before.
Stefan |
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Wed Apr 7 08:26:12 2021, Stefan Ritt, Unexpected noise in muxout: t_samp related?
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Dear Sean,
noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below
1 mV if the DRS4 input is clean (try to short it). |
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Fri Apr 9 20:55:28 2021, Stefan Ritt, Unexpected noise in muxout: t_samp related?
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If you do the cell calibration correctly, your noise should be ~0.4 mV. You seem to be 2-3x larger. The periodic negative spikes come if you dont'
sample at the right time. Adjust t_samp until they are gone.
Stefan |
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Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings?
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elog:824
Sean
Quinn wrote:
Dear DRS4 team, |
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Wed May 5 10:12:44 2021, Stefan Ritt, recording only timestamp and amplitude and/or filesize maximum
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The maximum file size depends on the underlying linux file system. Common values are 4-16 GBytes.
Stefan
Abaz |
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Mon Aug 9 12:50:31 2021, Stefan Ritt, C code to read the 4 channel with external trigger
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Sorry the late reply, I was on vacation.
Here are some answers:
1. I'm sorry I can't help much here, since I currently don't have a Windows 10 computer here to compile any code. I moved now completely |
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Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading
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The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what
could be wrong:
Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern |
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Sat Sep 18 15:48:30 2021, Stefan Ritt, drs_exam_multi with non-v4 boards, default configuration
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Hi,
please note the the evaluation board is what it says, a board to evaluate the chip, and is not meant for a full-blown shiny multi-board DAQ channel,
so support for that is kind of limited. |
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Thu Oct 14 15:25:07 2021, Stefan Ritt, livetime (or deadtime) of DRS4 evaluation board
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The one thing you can do easily is to look at the scaler values. If one channel counts all physical events, and you have all read out events, then the
ratio give you the live/deadtime. The hardware scalers also keep running during the DRS readout.
Stefan |
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Thu Oct 14 18:42:31 2021, Stefan Ritt, livetime (or deadtime) of DRS4 evaluation board
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I would say not exactly, but it's a good approximation.
Keita
Mizukoshi wrote:
Thank you very much for your response. |
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Tue Oct 26 12:00:51 2021, Stefan Ritt, External trigger and drs_exam
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1. Why should your waveform start from 0 to 5ns? I don't get your point. Whenever you trigger a readout, you get a 200ns wide time window, and by
definition it starts at zero.
2. In the software distribution you have a drs_exam_2048.cpp program. Note that your board needs to be physically modified before delivery to |
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Tue Oct 26 12:02:56 2021, Stefan Ritt, Trigger multiple boards independently
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Unfortunately an independent operation from a single computer is not supported by the software. You can try to modify the drs_exam program and extend
it. You can poll all boards in sequence and just read out that one which got a trigger, then start the loop again. But I don't know how good you are
in programming. I needs a bit of experience to do that. |
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Wed Oct 27 08:11:42 2021, Stefan Ritt, Trigger multiple boards independently
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I'm not sure if the rate would go up to 2 kHz (not 2 GHz!). Depends how the USB hub is designed. What you can do however is to buy 4 RaspberryPis
(total cost 150$) and run everythign in parallel. The evaluation boards works nicely with the Pi's.
Javier |
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Tue Nov 16 08:51:14 2021, Stefan Ritt, V3 board, only one channel works, all components at each channel input working
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A V3 boards is already 10 years old and out of warranty. The software has no configuration to turn channels off except the channel buttons on the main
page on top of the sliders. I presume the channels are broked due to some overvoltage applied to them (the V5 board is better protected against over voltage).
You can send it the board for repair, but it will cost almost the same amount of money than buying a new boards. |
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Mon Jan 3 17:13:41 2022, Stefan Ritt, DRS4 request assistance
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1. fDOMINO is defined as fREFCLK * 2048
2. Good values can be derived from the evaluation board schematics: C1=4.7nF, C2=1nF, R=130 Ohm
3. A "1" means a logical high level. See Wikipedia: https://en.wikipedia.org/wiki/Logic_level |