DRS4 Forum
  DRS4 Discussion Forum, Page 38 of 45  Not logged in ELOG logo
    Reply  Thu Jan 25 06:10:52 2018, chen wenjun, drscl doesn't find eval board but drsosc does (Windows 7) 
Hi! Jim:

  It seems that I meet the same question with you ,and I am confused ,have you find out the reason about this problem?Or can you tell me
how you deal with it?
Entry  Tue May 13 19:34:58 2014, Luka Pavelic, drsosc binary to cern ROOT file conversion 
Hi,

Does anybody have program for conversion from binary or xml to cern ROOT *.root file?
    Reply  Tue May 13 19:39:36 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 


    
        
            Luka Pavelic wrote:
        
        
            
            Hi,
    Reply  Tue May 13 22:03:47 2014, Luka Pavelic, drsosc binary to cern ROOT file conversion 
Thank you for your fast and very helpful replay.

I made it work with drsosc version 4 but with version 5 i am getting weird results. Is it possible that they changed binary formatting?
    Reply  Tue May 13 23:08:50 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 


    
        
            Luka Pavelic wrote:
        
        
            
            Thank you for your fast and very helpful replay.
    Reply  Fri Jun 27 11:23:19 2014, ChengMing Du, drsosc binary to cern ROOT file conversion 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
    Reply  Wed Jul 30 17:05:38 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 


    
        
            ChengMing Du wrote:
        
        
            
            
            
Entry  Mon Apr 22 15:33:28 2013, Benjamin LeGeyt, effect of jitter/alignment between SRCLK and ADC clock 
Hello!
let me apologize in advance if this has already been covered somewhere and I missed it. 
    Reply  Mon Apr 22 15:52:53 2013, Stefan Ritt, effect of jitter/alignment between SRCLK and ADC clock adc_phase.jpg


    
        
            Benjamin LeGeyt wrote:
        
        
            
            Hello!
Entry  Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter 
Hi all

    Reply  Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter 


    
        
            lorenzo neri wrote:
        
        
            
            Hi all
Entry  Wed Nov 6 11:53:28 2013, Dmitry Hits, flickering screen for drsosc 
Hi,
 
I have install drs software on ASUS EeeBox with Ubuntu 12.04 LTS. When I try to use ./drsosc the oscilloscope window flickers. Can you suggest
    Reply  Wed Nov 6 12:25:31 2013, Stefan Ritt, flickering screen for drsosc 


    
        
            Dmitry Hits wrote:
        
        
            
            Hi,
    Reply  Mon Nov 18 11:20:15 2013, Dmitry Hits, flickering screen for drsosc 


    
        
            Stefan Ritt wrote:
        
        
            
            
            
Entry  Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading  
Hi Steffan,

    I have a question about how to acquire the stop channel: 

    Process:   Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger,
    Reply  Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading  
The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what
could be wrong:


Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern
    Reply  Fri Nov 5 01:10:25 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading  
 




Jiaolong
wrote:



Hi Steffan,
    Reply  Fri Nov 5 01:12:10 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading  
Thanks for your advice. The problem has been solved by setting the srin again while reading out from srout.




Stefan
Ritt wrote:



The problem must be on your side, since the Write Shift Register readout
Entry  Mon Oct 14 09:32:33 2019, Danyang, how to acquire the stop position with channel cascading Capture.PNG
Hi Steffan,

       In DSR4 DATASHEET Rev.0.9 Page13,  there is a paragraph "If the DRS4 is configured for channel cascading
or daisy chaining, it is necessary to know which the current channel is where the sampling has been stopped. This can be
    Reply  Mon Oct 14 10:14:46 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
You first set A3-A0, on the next clock cycle you issue pulses on srclk, and about 10ns after each clock pulse the output shows up at srout. Best is to
verity this with an oscilloscope.

The radout of the shift register is independent of the readout mode, so you can use with with MUXOUT as well.
ELOG V3.1.5-fe60aaf