| ID |
Date |
Author |
Subject |
Text |
 |
|
776
|
Mon Oct 14 11:45:06 2019 |
Danyang | how to acquire the stop position with channel cascading | I tried the
logic in my designed board. The results
are shown in the picture: Srout keeps low |
|
|
777
|
Mon Oct 14 12:56:13 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | Note that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins |
|
|
778
|
Mon Oct 14 13:44:26 2019 |
Danyang | how to acquire the stop position with channel cascading | Yes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b， A3-A0 |
|
|
779
|
Mon Oct 14 15:27:09 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | If you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT |
|
|
780
|
Tue Oct 15 08:14:17 2019 |
Danyang | how to acquire the stop position with channel cascading | Thanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.
Best Regards, |
|
|
112
|
Sat Feb 19 17:25:29 2011 |
S S Upadhya | how to synchronize Sampling frequency of two evaluation boards | Dear sir,
We have two evaluation boards of
DRS4. We would like to use 8 inputs to be |
|
|
113
|
Sat Feb 19 22:46:35 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
|
|
|
114
|
Mon Feb 21 08:10:31 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
|
|
|
115
|
Mon Feb 21 12:42:33 2011 |
S S Upadhya | how to synchronize Sampling frequency of two evaluation boards |
|
|
|
533
|
Mon Aug 29 09:36:34 2016 |
benjamin legeyt | increment write config register on the fly? | Hello,
I have a question about using the
write config register to enable/disable sampling |
|
|
534
|
Mon Aug 29 10:57:33 2016 |
Stefan Ritt | increment write config register on the fly? | The issue with "stopping at cell 767"
would also affect this mode of operation.
Furthermore, the DRS4 chip has only 10 bit |
|
|
535
|
Mon Aug 29 12:18:49 2016 |
benjamin legeyt | increment write config register on the fly? | If I may trouble you for a little more
information, the critical point then is
that there should not be any zeroes in the |
|
|
536
|
Mon Aug 29 12:51:48 2016 |
Stefan Ritt | increment write config register on the fly? | The problem is when you change the write
config register from 11111111 to 01111111,
or from 00001111 to 00000111, then the last |
|
|
317
|
Fri Dec 13 10:37:18 2013 |
Dmitry Hits | input protection in DRS4 evaluation board | Dear Stefan
Last month I was using a DRS4 evaluation
board to digitise the signal from the charged |
|
|
318
|
Fri Dec 13 11:37:58 2013 |
Stefan Ritt | input protection in DRS4 evaluation board |
|
|
|
837
|
Thu Oct 14 15:19:00 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board | Dear experts,
I would like to use the DRS4 evaluation |
|
|
838
|
Thu Oct 14 15:25:07 2021 |
Stefan Ritt | livetime (or deadtime) of DRS4 evaluation board | The one thing you can do easily is to look
at the scaler values. If one channel counts
all physical events, and you have all read |
|
|
839
|
Thu Oct 14 18:03:52 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board | Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the |
|
|
840
|
Thu Oct 14 18:42:31 2021 |
Stefan Ritt | livetime (or deadtime) of DRS4 evaluation board | I would say not exactly, but it's a
good approximation.
|
|
|
841
|
Fri Oct 15 06:15:53 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board | Thank you very much.
|
|