DRS4 Forum
  DRS4 Discussion Forum, Page 39 of 44  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
ID Date Authordown Subject Text Attachments
  319   Mon Dec 16 11:09:25 2013 Dmitry Hitssynchronisation of readouts of two boards for offline analysis

    

       
            
  
  367   Fri Sep 12 11:52:21 2014 Dmitry Hitssynchronizing two DRS4 evaluation boards readout with one computer Hi everyone,
Has anyone tried to synchronize 2
(two) DRS4 evaluation boards readout by the
  
  369   Fri Sep 12 13:37:42 2014 Dmitry Hitssynchronizing two DRS4 evaluation boards readout with one computer

    

       
            
  
  371   Fri Sep 12 14:57:22 2014 Dmitry Hitscompilation error for v5.0.2 Hi,
I am getting the following compilation
error when trying to compile version 5.0.2
  
  373   Fri Sep 12 16:38:24 2014 Dmitry Hitscompilation error for v5.0.2

    

       
            
  
  481   Mon Feb 29 13:33:06 2016 Dmitry Hitstwo DRS4 boards configuration with 2048 samples eachDear Stefan,

I daisy-chained two boards (master
sn#: 2514 - slave sn#: 2513) each with 2048
  
  520   Mon May 2 14:31:28 2016 Dmitry Hitstwo DRS4 boards configuration with 2048 samples eachHi Stefan

Any chance you have time to fix
the software for multiboard configuration
  
  865   Wed Feb 16 14:06:45 2022 Dmitry HitsSliders missing in drsoscHi everyone,

Did anyone have a "missing
sliders problem" in GUI (see attachment) 
 Screen_Shot_2022-02-14_at_14.17.30.png 
  638   Thu Nov 16 02:55:44 2017 Diego YankelevichAveraging capabilities The Display window in the Oscilloscope
software shows averaging capabilites but
I have not been able to activate these. Is
  
  645   Tue Dec 12 00:25:50 2017 Diego YankelevichExternal trigger using Raspberry PiDear Steffan:


We have been able to use the
DRS4 using a Raspberry Pi but we have not
  
  748   Thu Mar 14 03:43:49 2019 Deepak SamuelHow to buy DRS evaluation kitDear Stefan,

I have emailed drs4@psi.ch a couple
of times regarding the pricing of the evaluation
  
  724   Thu Nov 8 11:44:35 2018 Davide DepaoliTiming IssueHi,

We are using the DRS4 Evaluation Board as
  
  726   Thu Nov 8 12:02:34 2018 Davide DepaoliTiming IssueThanks a lot for the quick response.
We will do as you suggest.
  
  774   Mon Oct 14 09:32:33 2019 Danyanghow to acquire the stop position with channel cascadingHi Steffan,

       In DSR4
DATASHEET Rev.0.9 Page13,  there is
 Capture.PNG 
  776   Mon Oct 14 11:45:06 2019 Danyanghow to acquire the stop position with channel cascadingI tried the
logic in my designed board.  The results
are shown in the picture: Srout keeps low
 Capture.PNG 
  778   Mon Oct 14 13:44:26 2019 Danyanghow to acquire the stop position with channel cascadingYes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b, A3-A0
  
  780   Tue Oct 15 08:14:17 2019 Danyanghow to acquire the stop position with channel cascadingThanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.

Best Regards,
  
  542   Sun Oct 9 10:43:35 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/s(Board Type:9, DRS4)

Hello,

I´m trying to reach the timig
  
  544   Mon Oct 10 11:30:37 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/sHello Stefan,

Chn2 & Chn3 were used for delay-determination as
you can see on the second picture.
 allChannels_zero_scaled.pngChn2_Chn3_1ns_delay_scaled.png 
  546   Tue Oct 11 09:04:33 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/sHello Stefan,

thanks for the paper. That makes
sense. I thought about sth. like that but
  
ELOG V3.1.4-bcd7b50