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ID Date Authorup Subject
  641   Wed Nov 22 08:58:33 2017 chen wenjun using of the DRS Command Line Interface

OK!Thank you! One more question,when I use the Oscillocope ,I found that the actual speed is a constant value of 1.007G,how can change this speed.

Stefan Ritt wrote:

The command line interface is more a debugging tool for experts, and you are not supposed to use it except to test the connection to the evaluation board. The programs for the user are the DRS Oscilloscope and the drs_exam.cpp example program to read out the board with your own program.

Stefan

chen wenjun wrote:

Hello! I'm using DRS4 evaluation board V5 with the drs command line interface,but the mannal only explained the meaning of the command--"info".And I can't get the hang of the use of other commands through "help",so is there anywhere can I learn more about other commands?Or I can only learn it through the datasheet of DRS4 chip.

Thanks!

 

 

 

 

  643   Wed Nov 22 09:19:11 2017 chen wenjun using of the DRS Command Line Interface

Thank you very much !! All my fault for I thought it too comlicated. Thank you sincerely!

Stefan Ritt wrote:

Remove the check mark from the "Lock" box and enter a different value in the sampling speed box and hit return.

chen wenjun wrote:

OK!Thank you! One more question,when I use the Oscillocope ,I found that the actual speed is a constant value of 1.007G,how can change this speed.

Stefan Ritt wrote:

The command line interface is more a debugging tool for experts, and you are not supposed to use it except to test the connection to the evaluation board. The programs for the user are the DRS Oscilloscope and the drs_exam.cpp example program to read out the board with your own program.

Stefan

chen wenjun wrote:

Hello! I'm using DRS4 evaluation board V5 with the drs command line interface,but the mannal only explained the meaning of the command--"info".And I can't get the hang of the use of other commands through "help",so is there anywhere can I learn more about other commands?Or I can only learn it through the datasheet of DRS4 chip.

Thanks!

 

 

 

 

 

 

  771   Tue Aug 27 08:33:22 2019 chinmay basuDRS4

Is DRS4 suitable for use with Silicon surface barrier detectors?

  443   Fri Aug 7 18:41:37 2015 danteDRS4

Hi

I have just installed DRS4, but when I try to view it from the USB it don't work. Why?

 

  [  .../home  $] lsusb -d 04b4:1175 -v

Bus 002 Device 008: ID 04b4:1175 Cypress Semiconductor Corp.
Couldn't open device, some information will be missing
Device Descriptor:

  186   Thu Nov 1 20:08:33 2012 hongwei yangDRS4 firmware

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point? Or is there any drs4_eval4_app.vhd missing in the source files?

 

thanks

 

Hongwei

  188   Thu Nov 1 20:21:44 2012 hongwei yangDRS4 firmware

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

  189   Thu Nov 1 20:25:53 2012 hongwei yangDRS4 firmware

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

  191   Thu Nov 1 20:46:53 2012 hongwei yangDRS4 firmware

Stefan Ritt wrote:

hongwei yang wrote:

hongwei yang wrote:

Stefan Ritt wrote:

hongwei yang wrote:

Hi,

    We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.

could you help me find this trigger_config access point?

 

thanks

 

Hongwei

The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).

I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.

 

Best regards,

Stefan

 Ah, great, that helps, Thank you!

 

Hongwei

 By the way, will there be a drs4_eval4.vhd as well?

 Here it is.

 Thanks. have a good day

  315   Tue Dec 10 14:48:42 2013 ismail okan atakisimeasurement range

I m trying to measure lifetime in our lab and I intend to take
measurement with DRS4 at that point I have a little bit confused about
DRS4 time range.In My system I opened 10 us gate but after triggering
DRS4 measure nearly 1.2 us. Because of this I want to extend DRS4 time range that
measurement range from 1.2us to 10 us.  

  287   Tue Aug 27 16:14:49 2013 lengchongyang 

  Hello everyone!I'm a new user of DRS4 board,but it seems that some files are missing in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!

T

 

  288   Wed Aug 28 04:05:48 2013 lengchongyang 

lengchongyang wrote:

  Hello everyone!I'm a new user of DRS4 board,but it seems that some files are missing in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!

T

 

 I checked my project today and I think I need the file USR_LIB_VEC_IOFD_CPE_NALL.I don't know if is it a VHD files or a IP core.

I'll be extremely grateful.

  63   Tue Apr 13 10:45:18 2010 lorenzo nerievaluation board used like a counter

Hi all



it is possible to use the evaluation board like a counter?



I'm interested in the arriving time of all self trigger event in to a channel.



the input signal are 2V TTL of 10 ns at 50ohm, and the time acquisition window is 1 second.




can someone help me?



thanks in advance,



Lorenzo

  457   Wed Dec 23 15:38:14 2015 mony orbachDtap stops toggling after 40msec

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

  459   Thu Dec 24 10:51:31 2015 mony orbachDtap stops toggling after 40msec

my refclk is 1.25Mhz

what are the inputs and voltage you need to see?

Avdd and Dvdd are 2.5v

Denable is "1" Dwrite "0"

currently i am doing an external reset cycle, after that i am doing the configuration cycle.

should i relay on the internal reset?

the Dtap is toggling for 33.8msec and then just stops.

 

Thanks, Mony 

Stefan Ritt wrote:

No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?

mony orbach wrote:

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

 

 

  Draft   Sun Dec 27 15:06:59 2015 mony orbachDtap stops toggling after 40msec

Hi

We have some meesurs to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Ref+
  4. Dtap + Dspeed

From the screen shots it can be seen that ref+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

 

Stefan Ritt wrote:

I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.

Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem on your side.

 

Stefan

 

mony orbach wrote:

my refclk is 1.25Mhz

what are the inputs and voltage you need to see?

Avdd and Dvdd are 2.5v

Denable is "1" Dwrite "0"

currently i am doing an external reset cycle, after that i am doing the configuration cycle.

should i relay on the internal reset?

the Dtap is toggling for 33.8msec and then just stops.

 

Thanks, Mony 

Stefan Ritt wrote:

No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?

mony orbach wrote:

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

 

 

 

 

  462   Sun Dec 27 15:41:32 2015 mony orbachDtap stops toggling after 40msec

Hi

We have some measures to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Refck+
  4. Dtap + Dspeed

From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

 

Stefan Ritt wrote:

I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.

Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem on your side.

 

Stefan

 

mony orbach wrote:

my refclk is 1.25Mhz

what are the inputs and voltage you need to see?

Avdd and Dvdd are 2.5v

Denable is "1" Dwrite "0"

currently i am doing an external reset cycle, after that i am doing the configuration cycle.

should i relay on the internal reset?

the Dtap is toggling for 33.8msec and then just stops.

 

Thanks, Mony 

Stefan Ritt wrote:

No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?

mony orbach wrote:

Hi

the drs4 start to generate Dtap signal after reset and standard configuration.

while in reset Denable and  Dwrite are low

after reset we put Denable in high

the Dtap starts to toggle, and the plllck stabilizes on about 1V.  

After 40Msec the Dtap stops to toggle and the plllck go to 2.5V

Why do the Domino stop working?

 

Thanks, Mony

 

 

 

 

  464   Mon Dec 28 11:21:54 2015 mony orbachDtap stops toggling after 40msec

Hi Stefan

Thanks for your input.

We are in the process of assemble another PCB board.

so soon we can compere between two boards.

As for the PLLEN bit, we set it.

We checked several times the soldering of the DRS4 using a microscope.

Everything looks ok.

In what method do you recommend to solder the DRS4?

 

Thanks for the invitation to meet.

120Km is not so far J

 

mony

Stefan Ritt wrote:

Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins. So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually helps. Or remove the chip completely and try with another chip. In theory there is the possibility that the internal bond wire of the REFCLK signal has a bad connection, but we tested all chips we send out so we should have seen that. But trying with another chip cannot hurt in general. Next month I'm coming to the Weizman Institute for the ISOTDAQ shool. If you want we can meet there if you don't mind the 120 km drive from Haifa.

Stefan

mony orbach wrote:

Hi

We have some measures to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Refck+
  4. Dtap + Dspeed

From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

  465   Wed Dec 30 16:25:35 2015 mony orbachDtap stops toggling after 40msec

Hi

We have resolve the problem, the Dtap is now working correctly.

There were two problems:

  1. After configuration we put the all address bits to one (standby mode)

We are now setting the address bits to all zero. Failure

to do so result in Dtap  stop toggling after several hundred milliseconds.

  1. The DMODE bit in contradiction to the data sheet should be set to 0

And not to 1.

 

Is this a known bug in the chip?

Only bay setting DMODE to zero we got the Dtap to work correctly.

The PLL locks after 1 milisec.

If we set it to one we get Dtap that stop toggling after several hundred milliseconds.

We have test it on two boards, they both worked in the same.

Never did we get a One shot  Dtap.

 

Did you published a errata page to the drs4?

 

 

Thanks, Mony

 

mony orbach wrote:

Hi Stefan

Thanks for your input.

We are in the process of assemble another PCB board.

so soon we can compere between two boards.

As for the PLLEN bit, we set it.

We checked several times the soldering of the DRS4 using a microscope.

Everything looks ok.

In what method do you recommend to solder the DRS4?

 

Thanks for the invitation to meet.

120Km is not so far J

 

mony

Stefan Ritt wrote:

Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins. So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually helps. Or remove the chip completely and try with another chip. In theory there is the possibility that the internal bond wire of the REFCLK signal has a bad connection, but we tested all chips we send out so we should have seen that. But trying with another chip cannot hurt in general. Next month I'm coming to the Weizman Institute for the ISOTDAQ shool. If you want we can meet there if you don't mind the 120 km drive from Haifa.

Stefan

mony orbach wrote:

Hi

We have some measures to show (attached)

  1. Dtap and Denable
  2. Dtap+Denable in zoom
  3. Dtap + Refck+
  4. Dtap + Dspeed

From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)

And Dspeed is going done to zero after some time.

In our system Dspeed is shorted to pllout.

So it looks like pllout do not pump the RC filter capacitors.

We tested various value of R and C's.

Also we checked that pllout is sorted to Dspeed.

 

Thanks, mony

 

 

 

  473   Thu Jan 14 14:00:26 2016 mony orbachDtap stops toggling after 40msec

surrey i forgot to update..

after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111

after making shore that a0-a3 never get 1111 value thae drs4 woks as expected.

The dtap toggols ok.

We can sample and read all the data channels.

So, putting A0-A3 value of 1111 even for very short period  " confuse " the DRS and then it start to behave in a strange manner.

 

mony

Stefan Ritt wrote:

While I can understand 1., I'm puzzeled by 2.

If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This is clearly stated in the data sheet.

Concerning the DMODE bit, we operate all (!) our chips with DMODE=1. Actually this is the default value. After a reset, all register bits are "1", which enables the PLL and causes DTAP to oscillate. If DMODE=1, the DTAP signal should toggle only once (!) since the domino loop is not closed. So the scope traces you showed previously are consistent with the standby mode, but not possible with ANY setting of DMODE.

Stefan

mony orbach wrote:

Hi

We have resolve the problem, the Dtap is now working correctly.

There were two problems:

  1. After configuration we put the all address bits to one (standby mode)

We are now setting the address bits to all zero. Failure

to do so result in Dtap  stop toggling after several hundred milliseconds.

  1. The DMODE bit in contradiction to the data sheet should be set to 0

And not to 1.

 

Is this a known bug in the chip?

Only bay setting DMODE to zero we got the Dtap to work correctly.

The PLL locks after 1 milisec.

If we set it to one we get Dtap that stop toggling after several hundred milliseconds.

We have test it on two boards, they both worked in the same.

Never did we get a One shot  Dtap.

 

Did you published a errata page to the drs4?

 

Thanks, Mony

 

 

  33   Wed Feb 10 02:57:55 2010 pepe sanchez lopezHello

hello i am an student and i want to do my final project with drs4 board and i really can´t find how to open waveform file and how can i save or opened many of them quickly.

if you can tell me how i will be very grateful.

thanks,

kind regards.

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