DRS4 Forum
  DRS4 Discussion Forum, Page 40 of 44  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
ID Date Authorup Subject
  811   Fri Feb 26 17:05:26 2021 Tom SchneiderTrouble getting PLL to lock

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

  813   Fri Feb 26 18:33:52 2021 Tom SchneiderTrouble getting PLL to lock

Stefan,

Thanks for responding so quickly.  Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic).  BIAS is 0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the eval board.

Regarding the clock - I am not using an LVDS clock, but rather a 2.5V-level clock signal, with REFCLK- tied to 1.25V.  Sheet 9 of the datasheet states:  If no LVDS reference clock signal is available, a CMOS signal can be connected to REFCLK+ and the REFCLK input is connected to VDD/2 via a resistor divider.

Is that not a true statement?

-Tom
 

Stefan Ritt wrote:

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Tom Schneider wrote:

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

 

 

  815   Fri Feb 26 21:24:39 2021 Tom SchneiderTrouble getting PLL to lock

Probe capacitance makes that tricky - if I put my probe on DSPEED, I see that it starts at approx. 2.5V then gradually decreases until it hits 0V.  DTAP decreases from 3MHz to 0 during this time.

I'll try to get something together to show you.

Stefan Ritt wrote:

Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?

Tom Schneider wrote:

Stefan,

Thanks for responding so quickly.  Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic).  BIAS is 0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the eval board.

Regarding the clock - I am not using an LVDS clock, but rather a 2.5V-level clock signal, with REFCLK- tied to 1.25V.  Sheet 9 of the datasheet states:  If no LVDS reference clock signal is available, a CMOS signal can be connected to REFCLK+ and the REFCLK input is connected to VDD/2 via a resistor divider.

Is that not a true statement?

-Tom
 

Stefan Ritt wrote:

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Tom Schneider wrote:

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

 

 

 

 

  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lock

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

Stefan Ritt wrote:

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

 

  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lock

I found the problem, and it had nothing to do with the CMOS clock input.  As it turns out, even though I was using the default state of the config register, I still had to write to it after powerup.  Once I did that, the PLL locked immediately.

-Tom

Tom Schneider wrote:

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

Stefan Ritt wrote:

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

 

 

  350   Thu May 29 04:22:43 2014 Toshihiro NonakaCalibrationWaveform

I'm writing the drs_exam.cpp to use multi-boards(v3, firmware:4.0.0), and taking data succeeded. But I have several questions about function written in DRS.cpp.

 

  1. I wrote following code in drs_exam.cpp to set input range -0.4~0.6

                                     b1->SetInputRange(0.1);

            And the 100mV offset appeared(I attached a picture). I think this is due to the voltage calibration isn't done.(Calibrated to -0.5~0.5mV in DRS Oscilloscope)

            If so, could you show me a simple usage of "CalibrationWaveform()" function in DRS.cpp? (or other function?)

 

       2. Although this question might be the almost same with above, is there any way to execute voltage and timing calibration in drs_exam.cpp?

           Now I start DAQ by executing drs_exam.cpp after I execute voltage and timing calibration to each board by DRS Oscilloscope program.

 

      3. Which command is right to use external trigger?

                                   b1->SetTriggerSource(4);   or  b1->SetTriggerSource(1<<4);

 

Best regards,

Toshihiro Nonaka

Attachment 1: offset.png
offset.png
  514   Wed Apr 27 08:14:14 2016 Toshihiro Nonakaserial number problem

Dear all,

I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.

Recently however,  I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board.

Data taking can be done without any problems, but I'd like to know what is happening.

Any advice?

Thank you.

Toshihiro Nonaka

Attachment 1: serial.png
serial.png
  516   Wed Apr 27 09:51:37 2016 Toshihiro Nonakaserial number problem

The serial number has been fixed by using drscl. Thank you!

Stefan Ritt wrote:

If dis- and reconnecting the board does not help, there is the (small) chance that the serial number got erased in the board. You can re-set it with the "drscl" command line tool:

$ drscl
Found DRS4 board 0 on USB, serial #0, firmware revision 21305
B0> serial 2172

 

Toshihiro Nonaka wrote:

Dear all,

I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.

Recently however,  I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board.

Data taking can be done without any problems, but I'd like to know what is happening.

Any advice?

Thank you.

Toshihiro Nonaka

 

 

  623   Wed Jul 12 04:24:39 2017 Toshihiro NonakaTime resolution between boards

Hello,

I 'm using four evaluation boards v.3 to construct the multi-board DAQ system. One channel for each board is used as reference clock, then calibrate timing offline, which allow below 10ps resolution between boards.

Is it possible to keep the time resolution between boards below 10ps in daisy-chain mode with v.5 boards?

Thank you in adcance.

Best regards,

Toshihiro Nonaka

  651   Wed Jan 17 09:51:16 2018 Tran Cong ThienThe input signals recorded are different with the signal showed in oscilloscope

Dear Stefan,

I am using an DRS4 board to record the signals from an plastic scintillator detector. It was working really good, yet a few day ago the signals became "not right". When I checked the signal using an oscilloscope it show the normal signals previously recorded. The signal amplitude are clearly reduced (from 0.3 in oscilloscope to lower than 0.1 in DRS4). Can you show me how to show this problem?

Thank you very much!

Best Regards,

Thien 

  360   Wed Jul 30 11:38:58 2014 Tsutomu NagayoshiSampling speed of DRS4 Board ver4

 Hello!

I have a question concerning the sampling speed of the DRS4 evaluation board.

It is written in the manual that the sampling speed of  DRS4 Evaluation Board is supported above 0.7 GHz.

However I was able to set the sampling speed to be 0.5 GHz with the function DRSBpard::SetFrequency(0.5)  and realized that DRSBoard::GetTime function fills time array in every 2 ns.

I am wondering if the data taken with 0.5 GHz sampling is reliable or not.

 

Best regards,

Tsutomu Nagayoshi

 

 

  586   Tue Jan 31 01:37:35 2017 VO HONG HAILLD and ULD discriminations,
Dear Stefan, Is there any way to develop LLD and ULD discrimination in DSR-4 evaluation board? Best regards, V.H.Hai
  633   Tue Oct 17 14:58:58 2017 Vadym DenysenkoTime offset

Hello.

 

I have a simple question, can I set SetTriggerDelayNs() more than 1631 ns?

I need to set this delay to about 5 us... Can I do this? 

 

Thank you in advance! 

 

With best regards, 

Vadym

  635   Wed Oct 18 11:48:14 2017 Vadym DenysenkoTime offset

Thank you for your reply!

Stefan Ritt wrote:

No this is not possible. But you can delay your signal externally (like with a delay cable or electronically) and then send the dealyed signal to the evaluation board for triggering.

Stefan

Vadym Denysenko wrote:

Hello.

 

I have a simple question, can I set SetTriggerDelayNs() more than 1631 ns?

I need to set this delay to about 5 us... Can I do this? 

 

Thank you in advance! 

 

With best regards, 

Vadym

 

 

  625   Thu Jul 20 13:00:44 2017 Volodymyr RodinDriver installation on Windows 10

Dear Laura

You need to disable driver signature enforcement.  Then try again with path option.

 It helped me.

http://www.drivethelife.com/windows-drivers/how-to-disable-driver-signature-enforcement-on-windows-10-8-7-xp-vista.html

Best regards,

Volodymyr

Laura Gonella wrote:

Hello,

I am trying to get a DRS4 board to run on Windows 10. I am having problems with the driver installation. I am getting the follwoing message

"There is no driver selected for the device information set or element"

I had specified the path to look for the driver as C:\ProgramFilesx86\DRS\driver\. I also tried the option to look online for the driver. None works. Can anyone help?

Thanks,

Laura

 

  626   Fri Jul 21 09:16:02 2017 Volodymyr RodinTime output

Hello Stefan

I tried to convert binary to a simple txt file and found next problem - strange time output.

Here is output from little modification for read_binary.cpp (Its last output line also is strange: dT = -1.#IOns +- -1.$ps)

Found data for board #0
Found timing calibration for channel #1
Found boards#  1
     event    channel   waveform       time      point
         1          0  -0.000092   0.000000          0
         1          0   0.030548   0.000000          1
         1          0   0.059418   0.000000          2
         1          0   0.080200   0.000000          3
         1          0   0.094223   0.000000          4
         1          0   0.097702   0.000000          5
         1          0   0.094055   0.000000          6
         1          0   0.079117   0.000000          7
         1          0   0.060364   0.000000          8
         1          0   0.030960   0.000000          9
         1          0   0.000504   0.000000         10
         1          0  -0.031555   0.000000         11
         1          0  -0.057465   0.000000         12
         1          0  -0.080536   0.000000         13
         1          0  -0.095413   0.000000         14
         1          0  -0.099365   0.000000         15

I used output string in the following places, but it didn't help:

// reach channel data

:for (i=0 ; i<1024 ; i++) {
               // convert data to volts
               waveform[0][chn_index][i] = (voltage[i] / 65536. + eh.range/1000.0 - 0.5);
               // calculate time for this cell
               for (j=0,time[b][chn_index][i]=0 ; j<i ; j++)
                  time[b][chn_index][i] += bin_width[b][chn_index][(j+tch.trigger_cell) % 1024];

printf("%10d %10d %10f %10f %10d\n", eh.event_serial_number , chn_index , waveform[0][chn_index][i]  ,  time[0][chn_index][i]  , i);

And after alignment procedure:

t1 = time[b][0][(1024-tch.trigger_cell) % 1024];
         for (chn=1 ; chn<4 ; chn++) {
            t2 = time[b][chn][(1024-tch.trigger_cell) % 1024];
            dt = t1 - t2;
            for (i=0 ; i<1024 ; i++)
               time[b][chn][i] += dt;

printf("%10d %10d %10f %10f %10d\n", eh.event_serial_number , chn_index , waveform[0][chn_index][i]  ,  time[0][chn][i]  , i);
         }

Does it caused by some software or drivers changes?

Best regards,

Volodymyr

 

 

 

 

  627   Tue Jul 25 14:47:05 2017 Volodymyr RodinTime output

Hi again.

Okay, it works with 5.05 version very good and it is enough for me.

Besides,

What do I need to fix in this code for 2048 board?

Best wishes,

Volodymyr

Volodymyr Rodin wrote:

Hello Stefan

I tried to convert binary to a simple txt file and found next problem - strange time output.

Here is output from little modification for read_binary.cpp (Its last output line also is strange: dT = -1.#IOns +- -1.$ps)

Found data for board #0
Found timing calibration for channel #1
Found boards#  1
     event    channel   waveform       time      point
         1          0  -0.000092   0.000000          0
         1          0   0.030548   0.000000          1
         1          0   0.059418   0.000000          2
         1          0   0.080200   0.000000          3
         1          0   0.094223   0.000000          4
         1          0   0.097702   0.000000          5
         1          0   0.094055   0.000000          6
         1          0   0.079117   0.000000          7
         1          0   0.060364   0.000000          8
         1          0   0.030960   0.000000          9
         1          0   0.000504   0.000000         10
         1          0  -0.031555   0.000000         11
         1          0  -0.057465   0.000000         12
         1          0  -0.080536   0.000000         13
         1          0  -0.095413   0.000000         14
         1          0  -0.099365   0.000000         15

I used output string in the following places, but it didn't help:

// reach channel data

:for (i=0 ; i<1024 ; i++) {
               // convert data to volts
               waveform[0][chn_index][i] = (voltage[i] / 65536. + eh.range/1000.0 - 0.5);
               // calculate time for this cell
               for (j=0,time[b][chn_index][i]=0 ; j<i ; j++)
                  time[b][chn_index][i] += bin_width[b][chn_index][(j+tch.trigger_cell) % 1024];

printf("%10d %10d %10f %10f %10d\n", eh.event_serial_number , chn_index , waveform[0][chn_index][i]  ,  time[0][chn_index][i]  , i);

And after alignment procedure:

t1 = time[b][0][(1024-tch.trigger_cell) % 1024];
         for (chn=1 ; chn<4 ; chn++) {
            t2 = time[b][chn][(1024-tch.trigger_cell) % 1024];
            dt = t1 - t2;
            for (i=0 ; i<1024 ; i++)
               time[b][chn][i] += dt;

printf("%10d %10d %10f %10f %10d\n", eh.event_serial_number , chn_index , waveform[0][chn_index][i]  ,  time[0][chn][i]  , i);
         }

Does it caused by some software or drivers changes?

Best regards,

Volodymyr

 

 

 

 

 

  336   Wed Apr 16 03:22:43 2014 Wang why is the first channel output error?

 Hi,

 The diagram below is DRS4 output. Green is the output8+, blue is the output8-. Output8+ of the first channel is below  the baseline. It is not  right.

Others channel  is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code  is wrong. what reason is caused? Thanks!

Attachment 1: QQ??20140416090124.jpg
QQ??20140416090124.jpg
  340   Thu Apr 17 12:02:28 2014 Wang The first channel is wrong.

 Hi,

   I want to describe this phenomenon again. The diagram below is DRS4 output. There is no input signal. Green is the output8+, blue is the output8-. Output8+ of the first channel is below  the baseline. The output is saturation when input ADC. It is not right, and what is it  in front of the first channel? It seemed there are two channels.  Others channel  is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code  is wrong. What reason is caused? Can anyone help me to solve the problem? Thanks!

Attachment 1: QQ??20140417174309.jpg
QQ??20140417174309.jpg
  447   Tue Nov 3 22:37:56 2015 Will FlanaganLatest macro for DRS4 V5

Hi DRS4 Experts,

I have an extremely naive question: Is there any official macro to unpack the DRS4 binary files? All I am looking to do is to plot a few of my waveforms and manipulate them in root. I am using OSX 10.10 and ROOT 5.34.

Thanks in advance,

Will

ELOG V3.1.4-bcd7b50