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New entries since:Thu Jan 1 01:00:00 1970
ID Date Authorup Subject Text Attachments
  811   Fri Feb 26 17:05:26 2021 Tom SchneiderTrouble getting PLL to lockHello,

I am working on a custom PCB design
with the DRS4 chip, and I can't get the
  813   Fri Feb 26 18:33:52 2021 Tom SchneiderTrouble getting PLL to lockStefan,

Thanks for responding so quickly. 
Yes I have my clock source going to REFCLK+
  815   Fri Feb 26 21:24:39 2021 Tom SchneiderTrouble getting PLL to lockProbe capacitance makes that tricky - if
I put my probe on DSPEED, I see that it starts
at approx. 2.5V then gradually decreases
  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lockThats not a simple modification to my PCB,
but I'll give it a try.  Thanks
for your help
  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lockI found the problem, and it had nothing
to do with the CMOS clock input.  As
it turns out, even though I was using the
  350   Thu May 29 04:22:43 2014 Toshihiro NonakaCalibrationWaveformI'm writing the drs_exam.cpp to use multi-boards(v3,
firmware:4.0.0), and taking data succeeded.
But I have several questions about function
  514   Wed Apr 27 08:14:14 2016 Toshihiro Nonakaserial number problem Dear all,

I'm using 3 DRS boards simultaneously
and their serial numbers are 2169, 2170,
  516   Wed Apr 27 09:51:37 2016 Toshihiro Nonakaserial number problem The serial number has been fixed by
using drscl. Thank you!

  623   Wed Jul 12 04:24:39 2017 Toshihiro NonakaTime resolution between boardsHello,

I 'm using four evaluation
boards v.3 to construct the multi-board DAQ
  651   Wed Jan 17 09:51:16 2018 Tran Cong ThienThe input signals recorded are different with the signal showed in oscilloscope Dear Stefan,

I am using an DRS4 board to record
the signals from an plastic scintillator
  360   Wed Jul 30 11:38:58 2014 Tsutomu NagayoshiSampling speed of DRS4 Board ver4 Hello!
I have a question concerning the
sampling speed of the DRS4 evaluation board.
  586   Tue Jan 31 01:37:35 2017 VO HONG HAILLD and ULD discriminations,Dear Stefan,
 Is there any way to develop
LLD and ULD discrimination in DSR-4 evaluation
 Best regards,
  633   Tue Oct 17 14:58:58 2017 Vadym DenysenkoTime offset Hello.


I have a simple question, can I
  635   Wed Oct 18 11:48:14 2017 Vadym DenysenkoTime offset Thank you for your reply!

  625   Thu Jul 20 13:00:44 2017 Volodymyr RodinDriver installation on Windows 10Dear Laura

You need to disable driver signature
enforcement.  Then try again with path
  626   Fri Jul 21 09:16:02 2017 Volodymyr RodinTime outputHello Stefan

I tried to convert binary to a
simple txt file and found next problem -
  627   Tue Jul 25 14:47:05 2017 Volodymyr RodinTime outputHi again.

Okay, it works with 5.05 version very
good and it is enough for me.
  336   Wed Apr 16 03:22:43 2014 Wang why is the first channel output error?  Hi,
  340   Thu Apr 17 12:02:28 2014 Wang The first channel is wrong. Hi,  QQ??20140417174309.jpg 
  447   Tue Nov 3 22:37:56 2015 Will FlanaganLatest macro for DRS4 V5Hi DRS4 Experts,

I have an extremely naive question:
Is there any official macro to unpack the
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