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  544   Mon Oct 10 11:30:37 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/sHello Stefan,

Chn2 & Chn3 were used for delay-determination as
you can see on the second picture.
 allChannels_zero_scaled.pngChn2_Chn3_1ns_delay_scaled.png 
  545   Mon Oct 10 12:03:27 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sOk, I got it. The timing resolution is
affected by the signal-to-noise ratio over
the rise-time of your signal. You find the
 Screen_Shot_2016-10-10_at_12.01.03_.pngScreen_Shot_2016-10-10_at_12.01.57_.pngScreen_Shot_2016-10-10_at_12.36.48_.png 
  546   Tue Oct 11 09:04:33 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/sHello Stefan,

thanks for the paper. That makes
sense. I thought about sth. like that but
  
  547   Tue Oct 11 09:20:04 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sConcerning the offset, it looks to me like
you moved the offset slider slider of channel
1 to a non-zero position. You see that from
  
  548   Tue Oct 11 22:11:26 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sThank you very much! I will check it tomorrow!

-d

Concerning the offset, it looks
  
  412   Wed May 13 09:31:18 2015 Chenfei Yangtransparent-mode voltageHello Mr. Stefan Ritt

  For DRS4 differential inputs
ranges form 500mV to 1100mV, with ROFS set
 tek00000_.png 
  413   Wed May 13 09:45:51 2015 Stefan Ritttransparent-mode voltageThe ROFS signal has no effect in the transparent
mode, so you have to adjust O_OFS between
sampling and transparent mode accordingly.
  
  414   Wed May 13 09:55:09 2015 Chenfei Yangtransparent-mode voltageHere's the problem. My external ADC
has 2Vpp differtial input voltage range.
And the common-mode voltage of the inputs
  
  415   Wed May 13 10:16:40 2015 Stefan Ritttransparent-mode voltageI see your point. Actually I will soon
have the same issue since we design right
now a board with an AD9637 using the transparent
  
  416   Wed May 13 10:27:43 2015 Chenfei Yangtransparent-mode voltageI'm using an AD9252, 0.9V common mode
voltage is suggested and I already use 8
un-switchable level shifters. Just as you
  
  417   Wed May 13 12:34:49 2015 Stefan Ritttransparent-mode voltageThere might be a solution. How do you bias
th input of the
DRS4 chip? If you use a scheme as described
  
  418   Wed May 13 12:52:22 2015 Chenfei Yangtransparent-mode voltageYes. I use exactly the same scheme as you
mentioned. I'll try your solution.

  
  419   Wed May 13 16:13:07 2015 Chenfei Yangtransparent-mode voltageIf using a ROFS of 0.9V, the input would
not between 1.05V~2.05V better non-linearity
area. Is that appropriate?
  
  420   Wed May 13 16:25:24 2015 Stefan Ritttransparent-mode voltageTo get the good linearity, you need indeed
ROFS = 1.05V. With a O-OFS of 0.9V, a zero
input signal would give you DRS_OUT+=1.05V
  
  158   Tue Mar 20 16:23:33 2012 Martin Petriskatriger for measuring time between pulses in channels I have two BaF2 detectors with PMT
connected to Ch1 and Ch2. At this time Im
using external triger module to start DRS4.
  
  159   Tue Mar 20 16:33:50 2012 Stefan Ritttriger for measuring time between pulses in channels

    

       
            
  
  160   Wed Mar 21 09:33:00 2012 Martin Petriskatriger for measuring time between pulses in channels

    

       
            
  
  161   Wed Mar 21 09:39:33 2012 Stefan Ritttriger for measuring time between pulses in channels

    

       
            
  
  164   Wed Jun 20 10:40:21 2012 Ivan Petrovtriger for measuring time between pulses in channels

    

       
            
  
  165   Wed Jun 20 12:45:05 2012 Stefan Ritttriger for measuring time between pulses in channels

    

       
            
  
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