DRS4 Forum
  DRS4 Discussion Forum, Page 41 of 41  Not logged in ELOG logo
ID Dateup Author Subject
  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lock

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

Stefan Ritt wrote:

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

 

  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lock

I found the problem, and it had nothing to do with the CMOS clock input.  As it turns out, even though I was using the default state of the config register, I still had to write to it after powerup.  Once I did that, the PLL locked immediately.

-Tom

Tom Schneider wrote:

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

Stefan Ritt wrote:

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

 

 

  819   Fri Mar 5 09:39:42 2021 Stefan RittTrouble getting PLL to lock

That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros into the config register, thus disabling the PLL. Shame that I haven't thought of this before.

Stefan

  820   Wed Apr 7 03:29:39 2021 Sean QuinnUnexpected noise in muxout: t_samp related?

Dear DRS4 team,

I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are several items to address in the post.

First, I do not think the noise observed is being injected from elsewhere on the board. If I run the DRS in transparent mode, the baseline noise is low, on order 3.5 mV (60 ADU), perhaps radiated from a clock. See below image. The scale is 0 to 1000 ADU with LSB = 6 uV (same AD9245 as eval board.). The DRS is in RUNNING state, I have forced a trigger in the ILA. This is for a single channel, CH0, 1024 cells.

 

 

In the next image, I show the waveform obtained from a full readout. This corresponds to ADC_READOUT state, and the plot uses the same 1000 ADU scale. Noise seems around 350 ADU now, many factors worse than before.

We've spent a lot of time trying to understand what's happening. One area that would be helpful to get some guidance on is the "t_samp" parameter. In Fig. 11 of the data sheet, should there be a t_samp label between t_s and t_clk? It just has arrows there with some width.

 

 

In our current firmware I believe R1 is simply one clock after R0 (for both ROI and full readout mode). Would this lead to the added noise observed in muxout?

 

This leads to the next question on what to actually use for t_samp. In the data sheet, page 4 "Timing Characteristics" it says to use t_samp = t0 + t_clk. Additionally, t0= 10 ns from that table. Fair enough.

 

But if I check this against the eval board timing, I see very different values. Here the clock is 15 MHz so t_clk=67 ns (I note another post about this topic https://elog.psi.ch/elogs/DRS4+Forum/713), so I expect t_samp = 77 ns. But in practice it looks like the R0 to R1 delay is ~465 ns? (cyan=RSRLOAD, yellow=SRCLK)

Given this, is t_samp a value that should be tuned by the user?

 

Best regards,

Sean

 

  821   Wed Apr 7 08:26:12 2021 Stefan RittUnexpected noise in muxout: t_samp related?

Dear Sean,

noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below 1 mV if the DRS4 input is clean (try to short it).

The noise in the readout is expected. It looks exactly as Plot3 from the data sheet. You have to calibrate it away with a fixed offset for each cell as described in this paper: https://arxiv.org/abs/1405.4975 (paragraph IV. A. Voltage Calibration).

Concerning t_samp: Fig 11 in the datasheet just tells you that the rising edge of the SRCLK should come later than t_s after the address change. t_s is the setup time and 5 ns. Fig 12 tells you that the ADC should sample the analog output of the DRS t_samp after the address change A0-A3 and t_samp after the rising edge of SRCLK. 

The digitizing speed of the evaluation board is indeed 15 MHz instead of the maximum 30 MHz, because this was easier to program in the FPGA. The t_samp has to be there so that the analog output signal of the DRS4 settles to its final value after each SRCLK pulse. If you sample "too early", you sample with the ADC the output when it is sill moving. So you have to wait until the analog is settled, but just before the next DRS sample becomes visible at the output. You can fine tune this with a differential probe at the DRS4 analog output (on a single ended probe you might drown in noise) on one channel of yoru scope and the ADC sample clock on the other channel of your scope. Note that the ADC sample clock cannot be derived straight from your FPGA clock, but you need some clock manager to fine-adjust its phase in 1ns steps.

But again, looking at your output, everything seems fine. You see the 5mV rms noise indicated in the datasheet table 1, which translates to about 20 mV peak-to-peak. If you do the offset calibration, this should go down to below 1 mV.

Best,
Stefan

Sean Quinn wrote:

Dear DRS4 team,

I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are several items to address in the post.

First, I do not think the noise observed is being injected from elsewhere on the board. If I run the DRS in transparent mode, the baseline noise is low, on order 3.5 mV (60 ADU), perhaps radiated from a clock. See below image. The scale is 0 to 1000 ADU with LSB = 6 uV (same AD9245 as eval board.). The DRS is in RUNNING state, I have forced a trigger in the ILA. This is for a single channel, CH0, 1024 cells.

 

 

In the next image, I show the waveform obtained from a full readout. This corresponds to ADC_READOUT state, and the plot uses the same 1000 ADU scale. Noise seems around 350 ADU now, many factors worse than before.

We've spent a lot of time trying to understand what's happening. One area that would be helpful to get some guidance on is the "t_samp" parameter. In Fig. 11 of the data sheet, should there be a t_samp label between t_s and t_clk? It just has arrows there with some width.

 

 

In our current firmware I believe R1 is simply one clock after R0 (for both ROI and full readout mode). Would this lead to the added noise observed in muxout?

 

This leads to the next question on what to actually use for t_samp. In the data sheet, page 4 "Timing Characteristics" it says to use t_samp = t0 + t_clk. Additionally, t0= 10 ns from that table. Fair enough.

 

But if I check this against the eval board timing, I see very different values. Here the clock is 15 MHz so t_clk=67 ns (I note another post about this topic https://elog.psi.ch/elogs/DRS4+Forum/713), so I expect t_samp = 77 ns. But in practice it looks like the R0 to R1 delay is ~465 ns? (cyan=RSRLOAD, yellow=SRCLK)

Given this, is t_samp a value that should be tuned by the user?

 

Best regards,

Sean

 

 

  822   Fri Apr 9 20:22:13 2021 Sean QuinnUnexpected noise in muxout: t_samp related?

Hi Stefan,

 

Thanks much for the quick reply. Ok, yes, things do seem ok after the offset calibration. I am running into some other issues I could use your advice on but will make a separate thread. As a preview, you can see hints in this waveform (periodic negative spikes).

 This one should be considered resolved.

Stefan Ritt wrote:

Dear Sean,

noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below 1 mV if the DRS4 input is clean (try to short it).

The noise in the readout is expected. It looks exactly as Plot3 from the data sheet. You have to calibrate it away with a fixed offset for each cell as described in this paper: https://arxiv.org/abs/1405.4975 (paragraph IV. A. Voltage Calibration).

Concerning t_samp: Fig 11 in the datasheet just tells you that the rising edge of the SRCLK should come later than t_s after the address change. t_s is the setup time and 5 ns. Fig 12 tells you that the ADC should sample the analog output of the DRS t_samp after the address change A0-A3 and t_samp after the rising edge of SRCLK. 

The digitizing speed of the evaluation board is indeed 15 MHz instead of the maximum 30 MHz, because this was easier to program in the FPGA. The t_samp has to be there so that the analog output signal of the DRS4 settles to its final value after each SRCLK pulse. If you sample "too early", you sample with the ADC the output when it is sill moving. So you have to wait until the analog is settled, but just before the next DRS sample becomes visible at the output. You can fine tune this with a differential probe at the DRS4 analog output (on a single ended probe you might drown in noise) on one channel of yoru scope and the ADC sample clock on the other channel of your scope. Note that the ADC sample clock cannot be derived straight from your FPGA clock, but you need some clock manager to fine-adjust its phase in 1ns steps.

But again, looking at your output, everything seems fine. You see the 5mV rms noise indicated in the datasheet table 1, which translates to about 20 mV peak-to-peak. If you do the offset calibration, this should go down to below 1 mV.

Best,
Stefan

Sean Quinn wrote:

Dear DRS4 team,

I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are several items to address in the post.

First, I do not think the noise observed is being injected from elsewhere on the board. If I run the DRS in transparent mode, the baseline noise is low, on order 3.5 mV (60 ADU), perhaps radiated from a clock. See below image. The scale is 0 to 1000 ADU with LSB = 6 uV (same AD9245 as eval board.). The DRS is in RUNNING state, I have forced a trigger in the ILA. This is for a single channel, CH0, 1024 cells.

 

 

In the next image, I show the waveform obtained from a full readout. This corresponds to ADC_READOUT state, and the plot uses the same 1000 ADU scale. Noise seems around 350 ADU now, many factors worse than before.

We've spent a lot of time trying to understand what's happening. One area that would be helpful to get some guidance on is the "t_samp" parameter. In Fig. 11 of the data sheet, should there be a t_samp label between t_s and t_clk? It just has arrows there with some width.

 

 

In our current firmware I believe R1 is simply one clock after R0 (for both ROI and full readout mode). Would this lead to the added noise observed in muxout?

 

This leads to the next question on what to actually use for t_samp. In the data sheet, page 4 "Timing Characteristics" it says to use t_samp = t0 + t_clk. Additionally, t0= 10 ns from that table. Fair enough.

 

But if I check this against the eval board timing, I see very different values. Here the clock is 15 MHz so t_clk=67 ns (I note another post about this topic https://elog.psi.ch/elogs/DRS4+Forum/713), so I expect t_samp = 77 ns. But in practice it looks like the R0 to R1 delay is ~465 ns? (cyan=RSRLOAD, yellow=SRCLK)

Given this, is t_samp a value that should be tuned by the user?

 

Best regards,

Sean

 

 

 

  823   Fri Apr 9 20:29:45 2021 Sean QuinnSpikes/noise sensitive to clock settings?

Dear DRS4 team,

I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy data (post-calibration) with periodic spikes.

In the below plot

  • CH0 & CH1 are muon pulses from a scintillator + SiPM detector
  • CH8 is a 25 MHz sinewave (in phase with all generated board clocks)
  • Transparent mode = ON
  • ROI = OFF, "full readout mode", first sample = cell 0
  • DRS REFCLK = 1 MHz (2 GS/s)
  • ADC & SR CLK = 16 MHz, 0 deg. offset

 

After I modify some clock settings, things seem to improve dramatically, and the spike behavior changes

  • ADC and SR CLK = 15 MHz, 0 deg. offset
  • Transparent mode = ON
  • ROI = ON (just for testing purposes)
  • Add 1.064 ns skew to DRS REF CLK
  • NOTE: Unfortunately due to a design mishap, the ADC and FPGA clock use a phase-locked output pair on our clock synthesis chip, so we cannot fine-tune the skew for it.

Observed differences

  • Spike polarity seems inverted
  • Spikes limited to smaller number of cells now?
  • Spike amplitude reduced
  • Overall baseline variance seems better
  • New large positive spike artifact on CH0 that seems inverted on CH1
  • CH8 seems unaffected by large spikes?

Artifacts seem related to clock configuration, but I am sort of in the dark on what might be happening from a first-principles point of view. Any tips?

 

Warm regards,

Sean

  824   Fri Apr 9 20:55:28 2021 Stefan RittUnexpected noise in muxout: t_samp related?

If you do the cell calibration correctly, your noise should be ~0.4 mV. You seem to be 2-3x larger. The periodic negative spikes come if you dont' sample at the right time. Adjust t_samp until they are gone.

Stefan

Sean Quinn wrote:

Hi Stefan,

 

Thanks much for the quick reply. Ok, yes, things do seem ok after the offset calibration. I am running into some other issues I could use your advice on but will make a separate thread. As a preview, you can see hints in this waveform (periodic negative spikes).

 This one should be considered resolved.

Stefan Ritt wrote:

Dear Sean,

noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below 1 mV if the DRS4 input is clean (try to short it).

The noise in the readout is expected. It looks exactly as Plot3 from the data sheet. You have to calibrate it away with a fixed offset for each cell as described in this paper: https://arxiv.org/abs/1405.4975 (paragraph IV. A. Voltage Calibration).

Concerning t_samp: Fig 11 in the datasheet just tells you that the rising edge of the SRCLK should come later than t_s after the address change. t_s is the setup time and 5 ns. Fig 12 tells you that the ADC should sample the analog output of the DRS t_samp after the address change A0-A3 and t_samp after the rising edge of SRCLK. 

The digitizing speed of the evaluation board is indeed 15 MHz instead of the maximum 30 MHz, because this was easier to program in the FPGA. The t_samp has to be there so that the analog output signal of the DRS4 settles to its final value after each SRCLK pulse. If you sample "too early", you sample with the ADC the output when it is sill moving. So you have to wait until the analog is settled, but just before the next DRS sample becomes visible at the output. You can fine tune this with a differential probe at the DRS4 analog output (on a single ended probe you might drown in noise) on one channel of yoru scope and the ADC sample clock on the other channel of your scope. Note that the ADC sample clock cannot be derived straight from your FPGA clock, but you need some clock manager to fine-adjust its phase in 1ns steps.

But again, looking at your output, everything seems fine. You see the 5mV rms noise indicated in the datasheet table 1, which translates to about 20 mV peak-to-peak. If you do the offset calibration, this should go down to below 1 mV.

Best,
Stefan

Sean Quinn wrote:

Dear DRS4 team,

I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are several items to address in the post.

First, I do not think the noise observed is being injected from elsewhere on the board. If I run the DRS in transparent mode, the baseline noise is low, on order 3.5 mV (60 ADU), perhaps radiated from a clock. See below image. The scale is 0 to 1000 ADU with LSB = 6 uV (same AD9245 as eval board.). The DRS is in RUNNING state, I have forced a trigger in the ILA. This is for a single channel, CH0, 1024 cells.

 

 

In the next image, I show the waveform obtained from a full readout. This corresponds to ADC_READOUT state, and the plot uses the same 1000 ADU scale. Noise seems around 350 ADU now, many factors worse than before.

We've spent a lot of time trying to understand what's happening. One area that would be helpful to get some guidance on is the "t_samp" parameter. In Fig. 11 of the data sheet, should there be a t_samp label between t_s and t_clk? It just has arrows there with some width.

 

 

In our current firmware I believe R1 is simply one clock after R0 (for both ROI and full readout mode). Would this lead to the added noise observed in muxout?

 

This leads to the next question on what to actually use for t_samp. In the data sheet, page 4 "Timing Characteristics" it says to use t_samp = t0 + t_clk. Additionally, t0= 10 ns from that table. Fair enough.

 

But if I check this against the eval board timing, I see very different values. Here the clock is 15 MHz so t_clk=67 ns (I note another post about this topic https://elog.psi.ch/elogs/DRS4+Forum/713), so I expect t_samp = 77 ns. But in practice it looks like the R0 to R1 delay is ~465 ns? (cyan=RSRLOAD, yellow=SRCLK)

Given this, is t_samp a value that should be tuned by the user?

 

Best regards,

Sean

 

 

 

 

  825   Fri Apr 9 21:38:59 2021 Stefan RittSpikes/noise sensitive to clock settings?

elog:824

Sean Quinn wrote:

Dear DRS4 team,

I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy data (post-calibration) with periodic spikes.

In the below plot

  • CH0 & CH1 are muon pulses from a scintillator + SiPM detector
  • CH8 is a 25 MHz sinewave (in phase with all generated board clocks)
  • Transparent mode = ON
  • ROI = OFF, "full readout mode", first sample = cell 0
  • DRS REFCLK = 1 MHz (2 GS/s)
  • ADC & SR CLK = 16 MHz, 0 deg. offset

 

After I modify some clock settings, things seem to improve dramatically, and the spike behavior changes

  • ADC and SR CLK = 15 MHz, 0 deg. offset
  • Transparent mode = ON
  • ROI = ON (just for testing purposes)
  • Add 1.064 ns skew to DRS REF CLK
  • NOTE: Unfortunately due to a design mishap, the ADC and FPGA clock use a phase-locked output pair on our clock synthesis chip, so we cannot fine-tune the skew for it.

Observed differences

  • Spike polarity seems inverted
  • Spikes limited to smaller number of cells now?
  • Spike amplitude reduced
  • Overall baseline variance seems better
  • New large positive spike artifact on CH0 that seems inverted on CH1
  • CH8 seems unaffected by large spikes?

Artifacts seem related to clock configuration, but I am sort of in the dark on what might be happening from a first-principles point of view. Any tips?

 

Warm regards,

Sean

 

  826   Fri Apr 9 21:56:54 2021 Sean QuinnUnexpected noise in muxout: t_samp related?

Yes, there is some systematic board noise on this prototype, unfortunately sad

Ok, then it seems the other post I made might still belong in this thread after all.

Thanks for confirming negative spike behavior, we now have a mitigation plan going forward.

 

Cheers,

Stefan Ritt wrote:

If you do the cell calibration correctly, your noise should be ~0.4 mV. You seem to be 2-3x larger. The periodic negative spikes come if you dont' sample at the right time. Adjust t_samp until they are gone.

Stefan

Sean Quinn wrote:

Hi Stefan,

 

Thanks much for the quick reply. Ok, yes, things do seem ok after the offset calibration. I am running into some other issues I could use your advice on but will make a separate thread. As a preview, you can see hints in this waveform (periodic negative spikes).

 This one should be considered resolved.

Stefan Ritt wrote:

Dear Sean,

noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below 1 mV if the DRS4 input is clean (try to short it).

The noise in the readout is expected. It looks exactly as Plot3 from the data sheet. You have to calibrate it away with a fixed offset for each cell as described in this paper: https://arxiv.org/abs/1405.4975 (paragraph IV. A. Voltage Calibration).

Concerning t_samp: Fig 11 in the datasheet just tells you that the rising edge of the SRCLK should come later than t_s after the address change. t_s is the setup time and 5 ns. Fig 12 tells you that the ADC should sample the analog output of the DRS t_samp after the address change A0-A3 and t_samp after the rising edge of SRCLK. 

The digitizing speed of the evaluation board is indeed 15 MHz instead of the maximum 30 MHz, because this was easier to program in the FPGA. The t_samp has to be there so that the analog output signal of the DRS4 settles to its final value after each SRCLK pulse. If you sample "too early", you sample with the ADC the output when it is sill moving. So you have to wait until the analog is settled, but just before the next DRS sample becomes visible at the output. You can fine tune this with a differential probe at the DRS4 analog output (on a single ended probe you might drown in noise) on one channel of yoru scope and the ADC sample clock on the other channel of your scope. Note that the ADC sample clock cannot be derived straight from your FPGA clock, but you need some clock manager to fine-adjust its phase in 1ns steps.

But again, looking at your output, everything seems fine. You see the 5mV rms noise indicated in the datasheet table 1, which translates to about 20 mV peak-to-peak. If you do the offset calibration, this should go down to below 1 mV.

Best,
Stefan

Sean Quinn wrote:

Dear DRS4 team,

I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are several items to address in the post.

First, I do not think the noise observed is being injected from elsewhere on the board. If I run the DRS in transparent mode, the baseline noise is low, on order 3.5 mV (60 ADU), perhaps radiated from a clock. See below image. The scale is 0 to 1000 ADU with LSB = 6 uV (same AD9245 as eval board.). The DRS is in RUNNING state, I have forced a trigger in the ILA. This is for a single channel, CH0, 1024 cells.

 

 

In the next image, I show the waveform obtained from a full readout. This corresponds to ADC_READOUT state, and the plot uses the same 1000 ADU scale. Noise seems around 350 ADU now, many factors worse than before.

We've spent a lot of time trying to understand what's happening. One area that would be helpful to get some guidance on is the "t_samp" parameter. In Fig. 11 of the data sheet, should there be a t_samp label between t_s and t_clk? It just has arrows there with some width.

 

 

In our current firmware I believe R1 is simply one clock after R0 (for both ROI and full readout mode). Would this lead to the added noise observed in muxout?

 

This leads to the next question on what to actually use for t_samp. In the data sheet, page 4 "Timing Characteristics" it says to use t_samp = t0 + t_clk. Additionally, t0= 10 ns from that table. Fair enough.

 

But if I check this against the eval board timing, I see very different values. Here the clock is 15 MHz so t_clk=67 ns (I note another post about this topic https://elog.psi.ch/elogs/DRS4+Forum/713), so I expect t_samp = 77 ns. But in practice it looks like the R0 to R1 delay is ~465 ns? (cyan=RSRLOAD, yellow=SRCLK)

Given this, is t_samp a value that should be tuned by the user?

 

Best regards,

Sean

 

 

 

 

 

  827   Tue May 4 21:18:28 2021 Abaz Kryemadhirecording only timestamp and amplitude and/or filesize maximum

Hi,

I have been collecting some date using the DRS4 board at a trigger rate of 10-20 Hz,    I only need the timestamp and the amplitude, is there anyway to select only these two live as the data comes in to be stored. 

Alternatively,  What's the maximum file size or maximum number of events I can store in one binary file in linux. 

Thanks,

Best,

Abaz

  828   Wed May 5 10:12:44 2021 Stefan Rittrecording only timestamp and amplitude and/or filesize maximum

The maximum file size depends on the underlying linux file system. Common values are 4-16 GBytes.

Stefan

Abaz Kryemadhi wrote:

Hi,

I have been collecting some date using the DRS4 board at a trigger rate of 10-20 Hz,    I only need the timestamp and the amplitude, is there anyway to select only these two live as the data comes in to be stored. 

Alternatively,  What's the maximum file size or maximum number of events I can store in one binary file in linux. 

Thanks,

Best,

Abaz

 

  829   Wed Jul 14 14:55:09 2021 Mehrpad MonajemC code to read the 4 channel with external trigger

Hi there,

Recently I bought a 5GSPS evaluation board with 2048 sampling points.
I want to read 4 inputs of the evaluation bord ar 5 GSPS or 2.5GSP and use an external trigger.
I've checked your website and download drs-5.0.5 which contains the source code in C. It seems that the file drs_exam.cpp can do what I am looking for.
So far I could make and compile the project in Linux Ubuntu, but I couldn't compile it in Windows 10.  I've used Cygwin64 to compile the project in windows 10.

I have the following questions:

1- Since I only need to compile the drs_exam.cpp file, could please help me with how can I compile it directly(without making the entire project). Or tell me which version of Wxwidget and libusb I have to install.

2- If you have any sample code that can read 4 inputs with an external trigger, please tell me where can I find it.

In the end, I want to write a wrapper on this C file(which returns digitized data) and run it from my python program. Thank you in advance.
Best regards,
Mehrpad

 

  830   Mon Aug 9 12:50:31 2021 Stefan RittC code to read the 4 channel with external trigger

Sorry the late reply, I was on vacation. 

Here are some answers:

1. I'm sorry I can't help much here, since I currently don't have a Windows 10 computer here to compile any code. I moved now completely to MacOSX, being very similar to Linux. I'm not allowed to run a Windows 7 computer any more for security reasons. Last time this worked for me was with Wxwidget version 3.0 and libusb 1.0, but I guess libusb is not critical so you can use a newer version. If you just compile drs_exam.cpp, you don't need any Wxwidget library. That one is only used for the oscilloscope program.

2. The program drs_exam_2048.cpp is meant to read channels in 2048-bin mode.

3. To adjust the delay between the trigger and the readout, use the function b->SetTriggerDelayNs(xxx)

Best,
Stefan

Mehrpad Monajem wrote:

Hi there,

Recently I bought a 5GSPS evaluation board with 2048 sampling points.
I want to read 4 inputs of the evaluation bord ar 5 GSPS or 2.5GSP and use an external trigger.
I've checked your website and download drs-5.0.5 which contains the source code in C. It seems that the file drs_exam.cpp can do what I am looking for.
So far I could make and compile the project in Linux Ubuntu, but I couldn't compile it in Windows 10.  I've used Cygwin64 to compile the project in windows 10.

I have the following questions:

1- Since I only need to compile the drs_exam.cpp file, could please help me with how can I compile it directly(without making the entire project). Or tell me which version of Wxwidget and libusb I have to install.

2- If you have any sample code that can read 4 inputs with an external trigger, please tell me where can I find it.

In the end, I want to write a wrapper on this C file(which returns digitized data) and run it from my python program. Thank you in advance.
Best regards,
Mehrpad

 

 

  831   Tue Aug 10 13:57:09 2021 Mehrpad MonajemC code to read the 4 channel with external trigger

Thank you for the reply.

In the version that I have, I cannot find drs_exam_2048.cpp file. Could you please send me the link to download the software folder, which contain this file.

Best,

Mehrpad

Stefan Ritt wrote:

Sorry the late reply, I was on vacation. 

Here are some answers:

1. I'm sorry I can't help much here, since I currently don't have a Windows 10 computer here to compile any code. I moved now completely to MacOSX, being very similar to Linux. I'm not allowed to run a Windows 7 computer any more for security reasons. Last time this worked for me was with Wxwidget version 3.0 and libusb 1.0, but I guess libusb is not critical so you can use a newer version. If you just compile drs_exam.cpp, you don't need any Wxwidget library. That one is only used for the oscilloscope program.

2. The program drs_exam_2048.cpp is meant to read channels in 2048-bin mode.

3. To adjust the delay between the trigger and the readout, use the function b->SetTriggerDelayNs(xxx)

Best,
Stefan

Mehrpad Monajem wrote:

Hi there,

Recently I bought a 5GSPS evaluation board with 2048 sampling points.
I want to read 4 inputs of the evaluation bord ar 5 GSPS or 2.5GSP and use an external trigger.
I've checked your website and download drs-5.0.5 which contains the source code in C. It seems that the file drs_exam.cpp can do what I am looking for.
So far I could make and compile the project in Linux Ubuntu, but I couldn't compile it in Windows 10.  I've used Cygwin64 to compile the project in windows 10.

I have the following questions:

1- Since I only need to compile the drs_exam.cpp file, could please help me with how can I compile it directly(without making the entire project). Or tell me which version of Wxwidget and libusb I have to install.

2- If you have any sample code that can read 4 inputs with an external trigger, please tell me where can I find it.

In the end, I want to write a wrapper on this C file(which returns digitized data) and run it from my python program. Thank you in advance.
Best regards,
Mehrpad

 

 

 

  832   Mon Sep 6 14:42:23 2021 Jiaolonghow to acquire the stop channel with 2x4096 cascading

Hi Steffan,

    I have a question about how to acquire the stop channel: 

    Process:   Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, set A3-A0 to 1101, sclk keeps 0.

    Result:   the WSROUT pin keeps 0, the SROUT pin has no clock pulse as written in datasheet, but keeps always 1 or 0. It can be seen the stop channel is channel 0 or channel 1, but no situation to represtent channel 3 or channel 4. And if set sclk with 8 pulses, the  WSROUT and SROUT both keep 0.

    What should I pay attention to? Looking forward to your reply.

Jiaolong 

  833   Thu Sep 16 19:04:06 2021 Patrick Moriishi Freemandrs_exam_multi with non-v4 boards, default configuration

Hello, 

I made a modified version drs_exam_multi.cpp, but ran into an issue when running.  When I ran it, it only found the two boards with lower serial numbers (2781 and 2879) and complained that the others (2880 and 2881) were not v4. Would there be a simple workaround for this type of thing? Also, would I be able to use the .dat format to keep the file sizes down. 

If not, I am curious if there is a way I can at least set a default configuration for the drsosc program. It seems the drsosc.cfg is written when drsosc starts? Does it load the configuration from somewhere else? It would be very helpful to keep the same settings between runs, in particular the trigger delays, levels, trigger mode, and voltage offsets. Maybe I can even do this with just a few of the CLI commands? I know this is for experts only, but I think I would just need a few commands (setTrig, setTrigMode,  setTrigDelay, that sort of thing) if they do exist. I would check the help now, but I'm running, and I'm pretty sure I saw some for trigger settings. 

Anyhow, any help is appreciated in creating a more repeatable and automated data acquisition. Thanks!

 

  834   Sat Sep 18 15:47:50 2021 Stefan Ritthow to acquire the stop channel with 2x4096 cascading

The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what could be wrong:

  • Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern at WSROUT.
  • Do all tests with an oscilloscope, to avoid potential problems in your FPGA firmware (like an input configures as an output by mistake).
  • DWRITE must be high to see the contents of the WSR at the WSROUT pin, maybe that’s your mistake, see datasheet p 5 of 16.
  • To see the contents of the WSR at SROUT, A0-3 must be 1101b, please check with your oscilloscope
  • The addresses A0-A3 are simply connected to a multiplexer, so no clock is necessary after the addresses change

Stefan

Jiaolong wrote:

Hi Steffan,

    I have a question about how to acquire the stop channel: 

    Process:   Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, set A3-A0 to 1101, sclk keeps 0.

    Result:   the WSROUT pin keeps 0, the SROUT pin has no clock pulse as written in datasheet, but keeps always 1 or 0. It can be seen the stop channel is channel 0 or channel 1, but no situation to represtent channel 3 or channel 4. And if set sclk with 8 pulses, the  WSROUT and SROUT both keep 0.

    What should I pay attention to? Looking forward to your reply.

Jiaolong 

 

  835   Sat Sep 18 15:48:30 2021 Stefan Rittdrs_exam_multi with non-v4 boards, default configuration

Hi,

please note the the evaluation board is what it says, a board to evaluate the chip, and is not meant for a full-blown shiny multi-board DAQ channel, so support for that is kind of limited.

Strange that you only find two out of four boards. What happens if you disconnect the two boards the system finds and then try again? Might be that your USB hub does not have enough power to supply four boards (each taking 2.5W, so you need 10W in total). Unplugging some board will show you if you have a power problem.

The drsosc.cfg stores the current configuration. For this to work, the drsosc program has to have write access to the directory where the drsosc.cfg program is stored, which is usually the directory from where the program is started. Maybe you have to adjust permissions. Yes you have commands to set everything, just look into drs_exam.cpp and you will find most of them.

Best,
Stefan

Patrick Moriishi Freeman wrote:

Hello, 

I made a modified version drs_exam_multi.cpp, but ran into an issue when running.  When I ran it, it only found the two boards with lower serial numbers (2781 and 2879) and complained that the others (2880 and 2881) were not v4. Would there be a simple workaround for this type of thing? Also, would I be able to use the .dat format to keep the file sizes down. 

If not, I am curious if there is a way I can at least set a default configuration for the drsosc program. It seems the drsosc.cfg is written when drsosc starts? Does it load the configuration from somewhere else? It would be very helpful to keep the same settings between runs, in particular the trigger delays, levels, trigger mode, and voltage offsets. Maybe I can even do this with just a few of the CLI commands? I know this is for experts only, but I think I would just need a few commands (setTrig, setTrigMode,  setTrigDelay, that sort of thing) if they do exist. I would check the help now, but I'm running, and I'm pretty sure I saw some for trigger settings. 

Anyhow, any help is appreciated in creating a more repeatable and automated data acquisition. Thanks!

 

 

ELOG V3.1.4-80633ba