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New entries since:Thu Jan 1 01:00:00 1970
    Reply  Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5 
Entry  Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform 
Entry  Thu Oct 6 15:23:18 2016, Will Flanagan,  
Entry  Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps? 
Entry  Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs 
Entry  Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width bin_width_5gsps.jpgtest5gsps.dat
Entry  Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing 
    Reply  Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing 
Entry  Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing 
    Reply  Wed Dec 20 15:30:38 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp 
    Reply  Wed Dec 20 16:30:45 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp 
Entry  Thu May 12 05:18:47 2016, Yu, Problem For Software Download 
Entry  Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors 
Entry  Fri Feb 22 11:46:17 2013, Yury Golod, DRS4 trigger, different polarity 
Entry  Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support 
Entry  Mon Jul 14 19:03:05 2014, Yves Bianga, change cascading from 1024 to 2048 bins for each input channel 
Entry  Tue Aug 28 17:52:45 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
    Reply  Wed Aug 29 16:42:42 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
    Reply  Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
Entry  Thu Oct 4 20:50:36 2012, Zach Miller, DRS5 
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