| ID |
Date |
Author |
Subject |
Text |
 |
|
357
|
Fri Jun 27 11:23:19 2014 |
ChengMing Du | drsosc binary to cern ROOT file conversion |
|
|
|
412
|
Wed May 13 09:31:18 2015 |
Chenfei Yang | transparent-mode voltage | Hello Mr. Stefan Ritt
For DRS4 differential inputs
ranges form 500mV to 1100mV, with ROFS set |
|
|
414
|
Wed May 13 09:55:09 2015 |
Chenfei Yang | transparent-mode voltage | Here's the problem. My external ADC
has 2Vpp differtial input voltage range.
And the common-mode voltage of the inputs |
|
|
416
|
Wed May 13 10:27:43 2015 |
Chenfei Yang | transparent-mode voltage | I'm using an AD9252, 0.9V common mode
voltage is suggested and I already use 8
un-switchable level shifters. Just as you |
|
|
418
|
Wed May 13 12:52:22 2015 |
Chenfei Yang | transparent-mode voltage | Yes. I use exactly the same scheme as you
mentioned. I'll try your solution.
|
|
|
419
|
Wed May 13 16:13:07 2015 |
Chenfei Yang | transparent-mode voltage | If using a ROFS of 0.9V, the input would
not between 1.05V~2.05V better non-linearity
area. Is that appropriate? |
|
|
441
|
Mon Jul 20 09:25:38 2015 |
Chenfei Yang | Measure the time between different samples | Hi,
I have a question using a data acquisition
card base on DRS4 chip. How can I measure |
|
|
335
|
Tue Apr 15 18:35:41 2014 |
Carlo Stella | drs_exam project fail to compile | Hi,
when I try to compile drs_exam project
my computer give me this output: |
|
|
341
|
Thu Apr 24 23:03:25 2014 |
Carlo Stella | drs_exam project fail to compile |
|
|
|
761
|
Sat Jul 13 01:00:15 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello,
I have recently obtained a DRS4
Evaluation Board (V5), but I am unable to |
|
|
763
|
Mon Jul 15 19:34:25 2019 |
Brendan Posehn | Evaluation Board Test Functionality | Hello Stefan,
Thanks for the quick reply. The
issue was a faulty SMA connector, should |
|
|
117
|
Thu Apr 14 18:23:53 2011 |
Bob Hirosky | Fixes to DOScreen.cpp for recent built on linux | Hello,
I was just building version 3.1.0 and ran |
|
|
237
|
Thu Apr 11 22:41:13 2013 |
Bill Ashmanskas | code/details for optimal DRS4 timing calibration? | Hi Stefan,
Is either some example code or a
detailed written description available for |
|
|
768
|
Mon Aug 19 23:01:22 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Hi Stefan,
We have for some time now been
using custom firmware on a custom board to |
|
|
770
|
Tue Aug 20 16:05:21 2019 |
Bill Ashmanskas | should one deassert DENABLE while writing the write-shift register? | Aha -- many thanks. I think what
tripped up my test logic is that the "done"
state in drs4_eval5_app.vhd that executes |
|
|
241
|
Mon Apr 22 15:33:28 2013 |
Benjamin LeGeyt | effect of jitter/alignment between SRCLK and ADC clock | Hello!
let me apologize in advance if this
has already been covered somewhere and I |
|
|
346
|
Fri May 16 14:04:47 2014 |
Benjamin LeGeyt | simultaneous writing and reading with region of interest mode? | Hello!
We're developing electronics based
on the DRS4 to read out a breast PET scanner |
|
|
132
|
Sat Oct 15 04:45:25 2011 |
Aurelien Bouvier | DRS4 eval board: readout rate | Hi,
Our setup uses a DRS4 evaluation
board (version 2.0). |
|
|
773
|
Fri Sep 13 15:27:41 2019 |
Arseny Rybnikov | Scaler / How to modify the firmware to change the scaler integration time | Hello,
We want to use the inner DRS4 counter(scaler)
within more than the 100ms integration |
|
|
14
|
Wed Oct 14 23:53:05 2009 |
Armin Kolb | DRS_exam using USB Evaluation Board with OS X | For the users using a Macintosh,
after several hours the Evaluation
Board is working on my Macintosh (intel). |
|