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Entry  Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register? 
    Reply  Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register? 
Entry  Mon Apr 22 15:33:28 2013, Benjamin LeGeyt, effect of jitter/alignment between SRCLK and ADC clock 
Entry  Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode? 
Entry  Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate 
Entry  Fri Sep 13 15:27:41 2019, Arseny Rybnikov, Scaler / How to modify the firmware to change the scaler integration time 
Entry  Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X Makefile
Entry  Mon Sep 23 09:22:52 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board 
    Reply  Mon Sep 23 09:51:48 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board 
Entry  Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root 
Entry  Fri Sep 16 22:06:07 2011, Andriy Zatserklyaniy, compilation error for version 4.0.0 on linux 
Entry  Tue Nov 19 04:33:22 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks 
    Reply  Tue Nov 19 21:49:37 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks 
    Reply  Sat Jun 23 00:29:52 2012, Andrey Kuznetsov, triger for measuring time between pulses in channels 
Entry  Wed May 8 06:07:52 2013, Andrey Kuznetsov, DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program 
    Reply  Wed May 8 19:50:01 2013, Andrey Kuznetsov, DRS4 installation on Windows 8 issues 
    Reply  Thu Jul 25 01:31:29 2013, Andrey Kuznetsov, Evaluation Board Behavior 
Entry  Wed Aug 28 13:07:51 2013, Andrey Kuznetsov, Some bug fixes and questions 
    Reply  Thu Sep 5 10:01:00 2013, Andrey Kuznetsov, Some bug fixes and questions 
    Reply  Mon Sep 9 06:49:36 2013, Andrey Kuznetsov, Some bug fixes and questions 
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