| ID |
Date |
Author |
Subject |
Text |
 |
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542
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Sun Oct 9 10:43:35 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | (Board Type:9, DRS4)
Hello,
I´m trying to reach the timig |
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543
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Sun Oct 9 11:39:18 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Can you post a screenshot of your measurement?
Stefan
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544
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Mon Oct 10 11:30:37 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
Chn2 & Chn3 were used for delay-determination as
you can see on the second picture. |
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545
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Mon Oct 10 12:03:27 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Ok, I got it. The timing resolution is
affected by the signal-to-noise ratio over
the rise-time of your signal. You find the |
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546
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Tue Oct 11 09:04:33 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
thanks for the paper. That makes
sense. I thought about sth. like that but |
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547
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Tue Oct 11 09:20:04 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Concerning the offset, it looks to me like
you moved the offset slider slider of channel
1 to a non-zero position. You see that from |
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548
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Tue Oct 11 22:11:26 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks |
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412
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Wed May 13 09:31:18 2015 |
Chenfei Yang | transparent-mode voltage | Hello Mr. Stefan Ritt
For DRS4 differential inputs
ranges form 500mV to 1100mV, with ROFS set |
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413
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Wed May 13 09:45:51 2015 |
Stefan Ritt | transparent-mode voltage | The ROFS signal has no effect in the transparent
mode, so you have to adjust O_OFS between
sampling and transparent mode accordingly. |
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414
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Wed May 13 09:55:09 2015 |
Chenfei Yang | transparent-mode voltage | Here's the problem. My external ADC
has 2Vpp differtial input voltage range.
And the common-mode voltage of the inputs |
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415
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Wed May 13 10:16:40 2015 |
Stefan Ritt | transparent-mode voltage | I see your point. Actually I will soon
have the same issue since we design right
now a board with an AD9637 using the transparent |
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416
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Wed May 13 10:27:43 2015 |
Chenfei Yang | transparent-mode voltage | I'm using an AD9252, 0.9V common mode
voltage is suggested and I already use 8
un-switchable level shifters. Just as you |
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417
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Wed May 13 12:34:49 2015 |
Stefan Ritt | transparent-mode voltage | There might be a solution. How do you bias
th input of the
DRS4 chip? If you use a scheme as described |
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418
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Wed May 13 12:52:22 2015 |
Chenfei Yang | transparent-mode voltage | Yes. I use exactly the same scheme as you
mentioned. I'll try your solution.
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419
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Wed May 13 16:13:07 2015 |
Chenfei Yang | transparent-mode voltage | If using a ROFS of 0.9V, the input would
not between 1.05V~2.05V better non-linearity
area. Is that appropriate? |
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420
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Wed May 13 16:25:24 2015 |
Stefan Ritt | transparent-mode voltage | To get the good linearity, you need indeed
ROFS = 1.05V. With a O-OFS of 0.9V, a zero
input signal would give you DRS_OUT+=1.05V |
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158
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Tue Mar 20 16:23:33 2012 |
Martin Petriska | triger for measuring time between pulses in channels | I have two BaF2 detectors with PMT
connected to Ch1 and Ch2. At this time Im
using external triger module to start DRS4. |
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159
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Tue Mar 20 16:33:50 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
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160
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Wed Mar 21 09:33:00 2012 |
Martin Petriska | triger for measuring time between pulses in channels |
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161
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Wed Mar 21 09:39:33 2012 |
Stefan Ritt | triger for measuring time between pulses in channels |
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