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ID Date Author Subject
212   Thu Dec 27 00:12:12 2012 Jinhong Wangvariation of sampling capacitors

Hi Stefan,

A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?

Best,

Jinhong

213   Thu Dec 27 09:49:17 2012 Stefan Rittvariation of sampling capacitors

 Jinhong Wang wrote: Hi Stefan, A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?  Best, Jinhong

The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.

Stefan

214   Thu Dec 27 18:15:14 2012 Jinhong Wangvariation of sampling capacitors

Stefan Ritt wrote:

 Jinhong Wang wrote: Hi Stefan, A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?  Best, Jinhong

The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.

Stefan

Great to know this! Thanks~

Jinhong

215   Fri Feb 1 17:43:48 2013 Jinhong Wangvariation of sampling capacitors

Jinhong Wang wrote:

Stefan Ritt wrote:

 Jinhong Wang wrote: Hi Stefan, A quick question, what is the typical variation of the sampling capacitors in DRS4?  Will this variation be significant to affect your sampling result?  Best, Jinhong

The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.

Stefan

Great to know this! Thanks~

Jinhong

Hi Dr. Stefan,

So the sampling capacitors store the input voltage instead of the charge. What about the readout circuits? I saw there is a buffer followed each sampling capacitor. Do you buffer the charge (like a charge sensitive amplifier)  or the voltage? From Fig.12, 14 in datasheet, it seems most probably the readout is a charging or discharging of a capacitor. Could you please add some comments on this?

Cheers,

Jinhong

216   Tue Feb 5 14:38:35 2013 Stefan Rittvariation of sampling capacitors

 Jinhong Wang wrote: Hi Dr. Stefan, So the sampling capacitors store the input voltage instead of the charge. What about the readout circuits? I saw there is a buffer followed each sampling capacitor. Do you buffer the charge (like a charge sensitive amplifier)  or the voltage? From Fig.12, 14 in datasheet, it seems most probably the readout is a charging or discharging of a capacitor. Could you please add some comments on this?  Cheers, Jinhong

The buffer buffers the voltage, not the charge. The curves in Fig. 12, 14 indicate that the voltage followers take some time until they settle.

Stefan

60   Mon Apr 5 17:50:39 2010 Heejong Kimversion 1.2 evaluation board with firmware 13279?
```Hi, Stefan,

I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware 13191.

Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.

Thanks,
Heejong

```
67   Wed Apr 14 16:34:28 2010 Stefan Rittversion 1.2 evaluation board with firmware 13279?

 Heejong Kim wrote: ```Hi, Stefan, I found that my collaborator bought 2 older version of evaluation board before. They are the version 1.2 in plastics case with firmware 13191. Can I upgrade the firmware from 13191 to 13279? I'm wondering if the older version of evaluation board is working with firmware 13279. Thanks, Heejong ```

I checked and there is no significant difference between the two revisions, so I would just leave it.

151   Sat Feb 4 11:59:26 2012 Zhongwei Duwhat sort of detectors for physical experiment the DRS4 used?

Hello.

We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the DRS4 can do more accurate than traditional charge integral circuit for charge measuring.

So we need to know what sort of detectors for physical experiment the DRS4 has been used in?

Can you give me some information? For example, Si strip array detector or CsI scintillator r ball detector ? PMT or APD ?

152   Mon Feb 6 08:15:38 2012 Stefan Rittwhat sort of detectors for physical experiment the DRS4 used?

 Zhongwei Du wrote: Hello. We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the DRS4 can do more accurate than traditional charge integral circuit for charge measuring. So we need to know what sort of detectors for physical experiment the DRS4 has been used in? Can you give me some information? For example, Si strip array detector or CsI scintillator r ball detector ? PMT or APD ?

DRS4 is used for PMTs and APDs. The minimal rise/fall time which can be recorded with the DRS4 on the evaluation boards is about 0.8ns (see elog:84). Concerning charge measurement, it depends on your integration time. If your signal is for example 20ns and you sample with 5 GSPS, you get actually 100 samples. You digitize with 12 bits, but the S/N ratio is more like 11.5 bits. But since you have 100 samples, the accuracy of the measurement scales with sqrt(100)=10. So you have more like 11.5+3 bits = 14-15 bits, or a SNR of 20'000. Now your signal usually does not have an amplitude of 1V, will be more like 100mV or so, in which case your SNR goes to 2000. But this still gives you a resolution of 1/2000 = 0.5 per mille.

We did tests with a Ge detector for spectroscopy applications, where we used a shaping time of 2 micro seconds, both with traditional electronics and the DRS4, integrating the signal over 2 micro seconds. Both gave a resolution of about 0.4%, indicating that the resolution was not limited by the DRS but by the detector.

Best regards,

Stefan

336   Wed Apr 16 03:22:43 2014 Wang why is the first channel output error?

Hi,

The diagram below is DRS4 output. Green is the output8+, blue is the output8-. Output8+ of the first channel is below  the baseline. It is not  right.

Others channel  is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code  is wrong. what reason is caused? Thanks!

338   Wed Apr 16 08:30:32 2014 Stefan Rittwhy is the first channel output error?

 Wang wrote: Hi,  The diagram below is DRS4 output. Green is the output8+, blue is the output8-. Output8+ of the first channel is below  the baseline. It is not  right. Others channel  is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code  is wrong. what reason is caused? Thanks!

You are funny. Just by looking at a scope picture I should know what is wrong at your FPGA code. Unfortunately I'm not a magician. I looks to me like you have 11 channels in your diagram, although the chip has only 9. What I would recommend is to put some input to each channel one at a time, like a 10 MHz sine wave. You should then see that sine wave for the single channel at the output and can correlate input vs. output. Maybe your address bits are wrong or the chip has a soldering problem.

/Stefan

ELOG V3.1.4-bcd7b50