 Sat Jan 28 14:11:58 2017, Danny Petschke, AND trigger problems
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Dear Stefan,
I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals
are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude |
 Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems
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In the evaluation board we use an ADCMP601 comparator, which has a setup and hold time of 4.6 ns. So a pulse which exceeds the threshold for less than
4.6 ns will not trigger the board. If you AND two signals together, an additional constraint might apply on the coincidence pulse. This is processed in
the FPGA, but once it becomes too short, it won't trigger the board as well. I never made a real measurement of that, but I would not be suprised if |
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Thu Jun 8 14:26:23 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
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Hello,
I work with the DRS4 Evaluation Board V5 and I have a problem with the software.
I have a problem with |
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Thu Jun 8 15:52:20 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?
Stefan
Rebecca |
Fri Jun 9 09:44:33 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels 
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Hello,
It seems that a coincidence with two fixed channels suddenly works. I don't know why.
Screenshot 1 shows the trigger settings for the coincidence with two channels. |
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Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Hi,
from our screenshots I see the following:
- you have sometimes a huge oscillation in your preamplifier. Fix this first before doing any waveform recording |
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Thu Aug 21 11:03:36 2014, Martin Petriska, 10GSps on DRS4 Evm with delay cables
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Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).
Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay
cable? |
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Tue Aug 26 12:32:21 2014, Stefan Ritt, 10GSps on DRS4 Evm with delay cables
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Martin Petriska wrote:
Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048). |
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Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
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Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
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Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
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Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |
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Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed
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Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
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Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS
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Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS)
= 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained
from DC offset Correction, hence 11.5 bit is for DC input, am i right? If true, what about ENOB for AC input in the whole analog bandwidth? thanks~ |
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Wed Jul 21 10:58:20 2010, Stefan Ritt, ENOB of DRS
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Jinhong Wang wrote:
Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip |
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Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource
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Hi
I have a question about the function SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp)
In the implementation there is the following comment: |
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Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource
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Your first assumption is correct, e.g.
source = 00000000'00000001 = 0x0001 ==> CH1
source = 00010001'00000000 = 0x1100 ==> CH1 and EXT |
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Sun May 26 13:08:52 2013, tmiron alon,
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Hallo,
I'm using DRS4 Evaluation Board Rev 4.0 and I'm trying to change the output of the samples to be an average of # measurements (1000
or even more) |
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Fri Jun 7 10:22:48 2013, Stefan Ritt,
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tmiron alon wrote:
Hallo, |
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Tue Aug 27 16:14:49 2013, lengchongyang,
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Hello everyone！I'm a new user of DRS4 board,but it seems that some files are missing
in my demo project.So I hope someone could help me by sending a correct VHDL hardware project to my Email:lcyiss900@gmail.com.Thanks in advance!
T |
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Wed Aug 28 04:05:48 2013, lengchongyang,
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lengchongyang wrote:
Hello everyone！I'm a new user of DRS4 |