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ID Date Authordown Subject
  586   Tue Jan 31 01:37:35 2017 VO HONG HAILLD and ULD discriminations,
Dear Stefan, Is there any way to develop LLD and ULD discrimination in DSR-4 evaluation board? Best regards, V.H.Hai
  360   Wed Jul 30 11:38:58 2014 Tsutomu NagayoshiSampling speed of DRS4 Board ver4

 Hello!

I have a question concerning the sampling speed of the DRS4 evaluation board.

It is written in the manual that the sampling speed of  DRS4 Evaluation Board is supported above 0.7 GHz.

However I was able to set the sampling speed to be 0.5 GHz with the function DRSBpard::SetFrequency(0.5)  and realized that DRSBoard::GetTime function fills time array in every 2 ns.

I am wondering if the data taken with 0.5 GHz sampling is reliable or not.

 

Best regards,

Tsutomu Nagayoshi

 

 

  651   Wed Jan 17 09:51:16 2018 Tran Cong ThienThe input signals recorded are different with the signal showed in oscilloscope

Dear Stefan,

I am using an DRS4 board to record the signals from an plastic scintillator detector. It was working really good, yet a few day ago the signals became "not right". When I checked the signal using an oscilloscope it show the normal signals previously recorded. The signal amplitude are clearly reduced (from 0.3 in oscilloscope to lower than 0.1 in DRS4). Can you show me how to show this problem?

Thank you very much!

Best Regards,

Thien 

  350   Thu May 29 04:22:43 2014 Toshihiro NonakaCalibrationWaveform

I'm writing the drs_exam.cpp to use multi-boards(v3, firmware:4.0.0), and taking data succeeded. But I have several questions about function written in DRS.cpp.

 

  1. I wrote following code in drs_exam.cpp to set input range -0.4~0.6

                                     b1->SetInputRange(0.1);

            And the 100mV offset appeared(I attached a picture). I think this is due to the voltage calibration isn't done.(Calibrated to -0.5~0.5mV in DRS Oscilloscope)

            If so, could you show me a simple usage of "CalibrationWaveform()" function in DRS.cpp? (or other function?)

 

       2. Although this question might be the almost same with above, is there any way to execute voltage and timing calibration in drs_exam.cpp?

           Now I start DAQ by executing drs_exam.cpp after I execute voltage and timing calibration to each board by DRS Oscilloscope program.

 

      3. Which command is right to use external trigger?

                                   b1->SetTriggerSource(4);   or  b1->SetTriggerSource(1<<4);

 

Best regards,

Toshihiro Nonaka

  514   Wed Apr 27 08:14:14 2016 Toshihiro Nonakaserial number problem

Dear all,

I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.

Recently however,  I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board.

Data taking can be done without any problems, but I'd like to know what is happening.

Any advice?

Thank you.

Toshihiro Nonaka

  516   Wed Apr 27 09:51:37 2016 Toshihiro Nonakaserial number problem

The serial number has been fixed by using drscl. Thank you!

Stefan Ritt wrote:

If dis- and reconnecting the board does not help, there is the (small) chance that the serial number got erased in the board. You can re-set it with the "drscl" command line tool:

$ drscl
Found DRS4 board 0 on USB, serial #0, firmware revision 21305
B0> serial 2172

 

Toshihiro Nonaka wrote:

Dear all,

I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.

Recently however,  I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board.

Data taking can be done without any problems, but I'd like to know what is happening.

Any advice?

Thank you.

Toshihiro Nonaka

 

 

  623   Wed Jul 12 04:24:39 2017 Toshihiro NonakaTime resolution between boards

Hello,

I 'm using four evaluation boards v.3 to construct the multi-board DAQ system. One channel for each board is used as reference clock, then calibrate timing offline, which allow below 10ps resolution between boards.

Is it possible to keep the time resolution between boards below 10ps in daisy-chain mode with v.5 boards?

Thank you in adcance.

Best regards,

Toshihiro Nonaka

  811   Fri Feb 26 17:05:26 2021 Tom SchneiderTrouble getting PLL to lock

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

  813   Fri Feb 26 18:33:52 2021 Tom SchneiderTrouble getting PLL to lock

Stefan,

Thanks for responding so quickly.  Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic).  BIAS is 0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the eval board.

Regarding the clock - I am not using an LVDS clock, but rather a 2.5V-level clock signal, with REFCLK- tied to 1.25V.  Sheet 9 of the datasheet states:  If no LVDS reference clock signal is available, a CMOS signal can be connected to REFCLK+ and the REFCLK input is connected to VDD/2 via a resistor divider.

Is that not a true statement?

-Tom
 

Stefan Ritt wrote:

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Tom Schneider wrote:

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

 

 

  815   Fri Feb 26 21:24:39 2021 Tom SchneiderTrouble getting PLL to lock

Probe capacitance makes that tricky - if I put my probe on DSPEED, I see that it starts at approx. 2.5V then gradually decreases until it hits 0V.  DTAP decreases from 3MHz to 0 during this time.

I'll try to get something together to show you.

Stefan Ritt wrote:

Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?

Tom Schneider wrote:

Stefan,

Thanks for responding so quickly.  Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic).  BIAS is 0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the eval board.

Regarding the clock - I am not using an LVDS clock, but rather a 2.5V-level clock signal, with REFCLK- tied to 1.25V.  Sheet 9 of the datasheet states:  If no LVDS reference clock signal is available, a CMOS signal can be connected to REFCLK+ and the REFCLK input is connected to VDD/2 via a resistor divider.

Is that not a true statement?

-Tom
 

Stefan Ritt wrote:

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Tom Schneider wrote:

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

 

 

 

 

  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lock

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

Stefan Ritt wrote:

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

 

  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lock

I found the problem, and it had nothing to do with the CMOS clock input.  As it turns out, even though I was using the default state of the config register, I still had to write to it after powerup.  Once I did that, the PLL locked immediately.

-Tom

Tom Schneider wrote:

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

Stefan Ritt wrote:

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

 

 

  858   Tue Jan 25 14:15:00 2022 Thomas M.Regarding measuring for a set time

Hello,

I'm working on a project wherein we're looking at photomultipliers. We've already acquired a DRS4 evaluation board with the intent of using it to gather our data.

I've looked at the source code for the software with the intent of maybe writing a patch to add additional functionality. I was hoping you could answer some quick questions in that regard.

Am I correct in assuming that drsosc and drscl are functionally equivalent regarding collecting data? We want to run the DRS4-EB for a predefined amount of time. However, the DRS4 scope application seems only to run for a predefined set of measurements. Have I got that right? Is there some reason to avoid running the DRS4-EB for a predefined amount of time that I should be aware of?

Appreciate any help you can provide. Thanks!

Kind regards,

Thomas

  860   Tue Jan 25 14:44:49 2022 Thomas M.Regarding measuring for a set time

Yes, you've got it exactly right. Thank you, that helps a lot! 

Thomas

Stefan Ritt wrote:

drsosc is a graphical application contiously acquiring data from the board, and drscl is a command line tool for debugging, as written in the manual.

The drsosc application runs indefinitely, but I guess you refer to saving data (by hitting the "Save" button in the drsosc application). Yes the save functionality has a number of events, since you cannot store data indefinitely, since your harddisk does not have indefinite space!

I kind of sense that you want to convert the "number of event to save" into "number of seconds or hours to save". This is not build into the drsosc application. It's all open source, so feel free to change the code. Alternatively, you can use the drs_exam.cpp program coming with the distribution, wich is a simpel C++ program reading the board. It has a for loop over 10 events, but you can change the code easily to run for a predetermined amount of time.

Stefan

Thomas M. wrote:

Am I correct in assuming that drsosc and drscl are functionally equivalent regarding collecting data? We want to run the DRS4-EB for a predefined amount of time. However, the DRS4 scope application seems only to run for a predefined set of measurements. Have I got that right? Is there some reason to avoid running the DRS4-EB for a predefined amount of time that I should be aware of?

 

  588   Fri Feb 24 17:34:28 2017 Tarik ZenginPassing parameters to drscl

Hi everyone,

I wonder if there is a way to pass parameters to drscl. What I specifically want to do is calling drscl from a shell script and read/save some data. I want to schedule a measurement. Therefore I need to call drscl from the command line using some parameters.

It would look something like this;

#!/bin/bash

for i in {0..100}

  do

    echo "Reading $i"

    ./drscl read 0 0 test.xml

    sleep 1

done

This doesn't work of course. drscl won't take arguments from the command line. Can you suggest a way to do this please?

Thank you.

  807   Wed Jan 20 12:14:49 2021 Taegyu Leedrs4 persistence

Dear all,

I have a question about the function that drs4 can perform.

Is there any function in drs4 that is analogous to that of "persistence display" in oscilloscope?? (accumulating pulses)

 

Thank you

  605   Sat Apr 15 03:48:31 2017 Strahinja LukicWave rotation during transfer from the board?

I don't know if this question is already documented elsewhere.

I am developing a DAQ code for the DRS evaluation board, v4 for a test beam experiment. I link parts of the existing DRS code as a library.

To understand the effect of various flags used in calls to the functions DRSBoard::GetTime() and DRSBoard::GetWave(), I performed several tests with the 100 MHz signal connected to the inputs of the chip (DRSBoard::EnableTcal()), and several tests with signals from scintillation counters.

My question is about the flag "adjustToClock" in the call to DRSBoard::GetWave(). From looking at the code, I expected it to cause the waveforms to be "rotated" to start from the trigger cell, in a similar way that the flag "rotated" in the call to DRSBoard::GetTime() does for the time array. However, "adjustToClock" seems to shift the waveforms wrongly. I.e., if I want both the time and the amplitude arrays "rotated"  to start from the trigger cell, I should set rotated=true for time and adjustToClock=false for the amplitude. This is also how these functions are called in e.g., Osci::ReadWaveforms().

Is this correct, and does this mean that the amplitude array is "rotated" already during the transfer from the board?

I am using DRS evaluation board serial #2733, firmware revision 30000.

Many thanks,

Strahinja

 

  607   Thu Apr 20 06:30:13 2017 Strahinja LukicWave rotation during transfer from the board?

Thanks.

Strahinja

Stefan Ritt wrote:

This is correct. Actually the amplitude array is rotated already inside the DRS4 chip. So the readout starts with the stop cell plus one. If you do not do anything, the waveform is already "rotated". If you want the waveform to start with physical cell #0, you have to "unrotate" it.

Stefan

Strahinja Lukic wrote:

Is this correct, and does this mean that the amplitude array is "rotated" already during the transfer from the board?

 

  657   Tue Feb 27 13:17:00 2018 Steven BlockWIndows Connection problem with drs507 SOLVED

Hello All,

I too have been struggling with trying to get the drs4 (507) to work on my windows machine and I found it to be a problem with the libusb library. My solution is as follows and has worked on multiple PC's. I ran this solution after I first plugged in the drs4 and installed 507.

Go to http://zadig.akeo.ie/ and install the corresponding software.

After that, you will need to plug in the DRS4 to your computer. From there go to ‘Options’, and select ‘List all Devices’.

Finally, choose the DRS4 evaluation board from the list and press install driver and let it run. You should be fine after that. 

Best,

Steven

  659   Tue Feb 27 16:34:26 2018 Steven BlockDRS4 Dead times

Hello All,

I am currently trying to figure out how to properly characterize the dead time of the DRS4 board. My most recent experiment to try and answer this question involved using an external trigger that can range from 1Hz to 2MHz. I fed this trigger into the DRS4 and collected 1000 samples with no input to any channels. I repeated this across the range of my external trigger by a factor of ten [10Hz, 100Hz, 1kHz...etc]. After I had saved these runs in XML format, I looked at the difference between timestamps on the events. Attached are my findings. Can someone offer an explanation for the periodic peaks? I am new to the DRS4 and don't really understand how it works. My guess is that there is a buffer that has to be emptied every so often, but if so, the buffer emptying time varies with the frequency of the trigger. I would ideally like to be able to know the relation of the dead time to a particular setting I change on the DRS4 such as locking the sampling speed or changing external trigger frequency. 

Best,

Steven

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