Thank you for your help Stefan. I will try to get the TC part isolated.

I'd like to be able to know which channel (0,1,2,3 or external) was responsible for the trigger.  DRSBoard::GetTriggerSource() seems to always return 1.  Is there a way to get this information?  Using the DRS4 evaluation board and software version 5.0.3.

Thanks,

Cosmin

I am trying to use 4 evaluation boards with a powered USB hub (since eventually, I will have to do this on a laptop).  It seems like destroying the DRS object is insufficent to properly close the boards when on the hub (i.e. I get usb read errors next time I run my program). When all the boards are plugged into the computer, all is fine.  This is on Linux using libusb1. My guess is something about resetting the port doesn't work properly (but maybe that's this particular hub's fault?).  Has anyone else experienced a similar issue. If not, can someone recommend a hub that is known to work?

Dear Stefan Ritt,

I am using a DRS4 v5 to do timing measurements of Positron lifetime. I use the DRS Oscilloscope with triggering on 2 channels when I have a coincidence. Attached is a picture with all the setting that I use. When I use the DRS4 for a long measurements of 5 million events for a couple of hours, the DRS Oscilloscope stops showing any signal .After the first restart of the program I get a strange signal which is at the bottom of the scope range of voltage picture below(in the picture I changed the vertical positions of the channels for better viewing). Only after a couple of DRS Oscilloscope restarts and USB reconnections do I get the results again.

I currently am using another DRS4 v5 and the same situation occurs again although with lower frequency.

What can I do to solve this problem?

thank you very much,

Daniel

Dear Stefan Ritt,

Yes I use Windows 7, If the DRS Oscilloscope program stays on for a couple of hours without saving the data, the problem will occur. It seems it happens more often when there is data writing and when the rate of events is slow, about 100 events per second, at high rates it almost doesn't happen. Can it be temperature related?

Daniel

At hight rates I worked with files of up to 20 GB so I don't think this is the problem.

I will try to run it under Ubuntu and see if i can recreate the problem.

Thank you very much for the quick responses and help.

I too have air conditioning in the room, not sure to which power line it is connected, but I'll try to check this aswell.

Thank you very much.

I don't know if it helps, but we measured the time resolution between two independendly running v3 boards using a single PC (latest software) in Linux. (http://arxiv.org/abs/1405.4975)

You start the DRS DAQ program with only one USB board connected, first. Afterwards connect the second board and start another session. If you externally trigger (global) both boards with less than 1 Hz, you can garantee that both programs save the same events independently (from two individual DRS boards).

Daniel

I also use Ubuntu 14.04 LTS and for my V3 borad I have to use drsosc 4.x or ealier to perform the calibration.

Hi Kyle,

If I remember right the negative sampling width happens only for 498 and at high sampling speeds. It is described in a paper from Stefan:

http://arxiv.org/pdf/1405.4975.pdf

or

“Novel Calibration Method for Switched Capacitor Arrays Enables Time Measurements With Sub-Picosecond Resolution”( IEEE Transactions on Nuclear Science 61 (2014),Nr. 6, 3607–3617)

(Board Type:9, DRS4)

Hello,

I´m trying to reach the timig resolution of about 2.5ps as written in the manual. 

My settings are:

5GSamples/s

+/-0.5V

I followed the instructions of the manual. The chip was warm and ran about 10h. Then, Timing- followed by Voltage-Calibration.

The test-signal is a splittet sine-wave of 20MHz (function-generator) brought on A0 and A1 (A1 signal is delayed by 1ns-cable).

I´ve been testing different trigger-logic: (Chn1 AND Chn2), (Chn1 OR Chn2) and only Chn1 or Chn2. 

Trigger-levels were changed too.

All setups show the same result of 1.009ns +/- 30-35ns (results from the DRS-Oscilloscope).

What is wrong from my side? 

Thanks a lot for your help

Hello Stefan,

Chn2 & Chn3 were used for delay-determination as you can see on the second picture.

The second picture shows all 4 Channels without any voltage input.

On Channel 4 streaks (red circle) occur often and Channel 1 has totally different Offset (Picture 1). 

Thanks

Hello Stefan,

thanks for the paper. That makes sense. I thought about sth. like that but wasn`t sure. Couldn´t check higher frequencies (limit of my function generator).

What do think about the other picture I attached yesterday where Chn1 shows a totally different offset than Chn2-4. Moreover Chn4 shows some streaks (red circle) ?

Best regards

Danny

 Dear Stefan,

I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude (pulse rise time is 2.5ns) pulses cannot anymore triggered above 4-5ns delay. It means there is a proportionality between the trigger level and the available range where 2 signals can be triggered in AND logic (Time-difference between 2 pulses). Do I anything misunderstand or is the time the comparator needs by higher trigger Levels for comparation longer than the 200ns at 5.12GSamp?

Board was timing and voltage calibrated before.

Thx

Danny

Hi Steffan,

       In DSR4 DATASHEET Rev.0.9 Page13,  there is a paragraph "If the DRS4 is configured for channel cascading or daisy chaining, it is necessary to know which the current channel is where the sampling has been stopped. This can be
determined by addressing the Write Shift Register withA3-A0 = 1101b and by applying clock pulses to the SRCLK input ...".

       My question is the timing details about srclk, srout, A3-A0 in the above control and its timing relation with stop shift register (Figure 15).  And can this configuration be used in the full readout mode with output MUXOUT?               

Best Regards,
Danyang (sun2222@mail.ustc.edu.cn)

I tried the logic in my designed board.  The results are shown in the picture: Srout keeps low when A3-A0  is set to 1101 and srclk is set as you mentioned. And the drs4 chip does not output sine wave in such configuration.

Srout signal only reacts after the rsrload signal is pulled high and A3-A0 is not 1101.  

The number of srclk is not enough?  Is there any recommended time to configure the command?

Best Regards,
Danyang

Yes, firstly I configured the chip with 4x2048 bins by setting the Write Shift Register to 01010101b， A3-A0 keeps 1101----> secondly I enabled the domino wave, wait  some time for stable,  A3-A0 keeps 1111  ---->thirdly stops the domino wave when the trigger comes, A3-A0 keeps 1101 (or 1010, 0000)----> forthly send the clock pulse to the srclk pin, A3-A0 keeps 1101,  srout pin keeps low----> fifthly enable rsrload, A3-A0 (0000-1000),  srout pin reacts nomally.   I think the cascading is worked when I checked the waveform on the oscilloscope. Is there any step I missed?

Best Regards,
Danyang

Thanks a lot. The problem is solved when A3-A0 is set 1101 and srclk keeps low.

Best Regards,
Danyang

Hi,

We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
We found a strange behavior in the saved files, more specifically the time difference between two consecutive points is not constant, also after the Timing Calibration.
As an example, I paste a piece of a xml file saved using the drsosc program, acquiring CH1 (open):
	
	---------------------------
	---[ START XML EXAMPLE ]---
	---------------------------
	
	<?xml version="1.0" encoding="ISO-8859-1"?>
	<!-- created by MXML on Thu Nov  8 11:13:27 2018 -->
	<DRSOSC>
	<Event>
	<Serial>1</Serial>
	<Time>2018/11/08 11:13:27.163</Time>
	<HUnit>ns</HUnit>
	<VUnit>mV</VUnit>
	<Board_2796>
	<Trigger_Cell>216</Trigger_Cell>
	<Scaler0>0</Scaler0>
	<CHN1>
	<Data>0.000,-1.0</Data>
	<Data>1.083,-1.0</Data>
	<Data>2.143,-1.0</Data>
	<Data>2.926,-1.0</Data>
	<Data>4.249,-0.1</Data>
	<Data>4.929,-0.6</Data>
	<Data>6.075,-0.4</Data>
	<Data>7.042,0.0</Data>
	<Data>8.299,0.2</Data>
	
	[...]
	
	-------------------------
	---[ END XML EXAMPLE ]---
	-------------------------

We found the same behavior saving events in the binary format, and then reading them with the read_binary.cpp

Is there a way to fix our issue?

Thanks a lot

Davide and Alessio

Thanks a lot for the quick response.
We will do as you suggest.

Best regards

Davide and Alessio

> That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters, which all have different 
propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins, 
> you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
> 
> Best,
> Stefan
> 
> 
> > Hi,
> > 
> > We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
> > We found a strange behavior in the saved files, more specifically the time difference between two consecutive points is not constant, also after the Timing Calibration.
> > As an example, I paste a piece of a xml file saved using the drsosc program, acquiring CH1 (open):
> > 	
> > 	---------------------------
> > 	---[ START XML EXAMPLE ]---
> > 	---------------------------
> > 	
> > 	<?xml version="1.0" encoding="ISO-8859-1"?>
> > 	<!-- created by MXML on Thu Nov  8 11:13:27 2018 -->
> > 	<DRSOSC>
> > 	<Event>
> > 	<Serial>1</Serial>
> > 	<Time>2018/11/08 11:13:27.163</Time>
> > 	<HUnit>ns</HUnit>
> > 	<VUnit>mV</VUnit>
> > 	<Board_2796>
> > 	<Trigger_Cell>216</Trigger_Cell>
> > 	<Scaler0>0</Scaler0>
> > 	<CHN1>
> > 	<Data>0.000,-1.0</Data>
> > 	<Data>1.083,-1.0</Data>
> > 	<Data>2.143,-1.0</Data>
> > 	<Data>2.926,-1.0</Data>
> > 	<Data>4.249,-0.1</Data>
> > 	<Data>4.929,-0.6</Data>
> > 	<Data>6.075,-0.4</Data>
> > 	<Data>7.042,0.0</Data>
> > 	<Data>8.299,0.2</Data>
> > 	
> > 	[...]
> > 	
> > 	-------------------------
> > 	---[ END XML EXAMPLE ]---
> > 	-------------------------
> > 
> > We found the same behavior saving events in the binary format, and then reading them with the read_binary.cpp
> > 
> > Is there a way to fix our issue?
> > 
> > Thanks a lot
> > 
> > Davide and Alessio