| ID |
Date |
Author |
Subject |
Text |
 |
|
604
|
Thu Apr 13 17:10:58 2017 |
Christian Farina | Stand-alone Time Calibration for PSI Board | Thank you for your help Stefan. I will
try to get the TC part isolated.
|
|
|
409
|
Wed May 13 00:52:51 2015 |
Cosmin Deaconu | Getting Trigger Source | I'd like to be able to know which channel
(0,1,2,3 or external) was responsible for
the trigger. DRSBoard::GetTriggerSource() |
|
|
410
|
Wed May 13 01:07:36 2015 |
Cosmin Deaconu | DRS4 Evaluation Board + Powered USB Hub | I am trying to use 4 evaluation boards
with a powered USB hub (since eventually,
I will have to do this on a laptop). |
|
|
485
|
Mon Mar 21 10:38:27 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run | Dear Stefan Ritt,
I am using a DRS4 v5 to do timing
measurements of Positron lifetime. I use |
|
|
501
|
Mon Apr 4 11:41:26 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run | Dear Stefan Ritt,
Yes I use Windows 7, If the DRS
Oscilloscope program stays |
|
|
506
|
Wed Apr 6 09:43:52 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run | At hight rates I worked with files of up
to 20 GB so I don't think this is the
problem. |
|
|
507
|
Wed Apr 6 09:46:10 2016 |
Daniel Dribin | DRS Oscilloscope freezing after a long run |
Martin Petriska |
|
|
400
|
Thu Mar 19 07:37:52 2015 |
Daniel Stricker-Shaver | Running 2 instances of a DRS DAQ program | I don't know if it helps, but we measured
the time resolution between two independendly
running v3 boards using a single PC (latest |
|
|
407
|
Tue Apr 21 13:03:38 2015 |
Daniel Stricker-Shaver | DRS4 Evaluation Board Baseline/Voltage Calibration | I also use Ubuntu 14.04 LTS and for my
V3 borad I have to use drsosc 4.x or ealier
to perform the calibration. |
|
|
511
|
Sat Apr 23 12:33:17 2016 |
Daniel Stricker-Shaver | Negative fCellDT values from GetTimeCalibration() | Hi Kyle,
If I remember right the negative
sampling width happens only for 498 and at |
|
|
542
|
Sun Oct 9 10:43:35 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | (Board Type:9, DRS4)
Hello,
I´m trying to reach the timig |
|
|
544
|
Mon Oct 10 11:30:37 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
Chn2 & Chn3 were used for delay-determination as
you can see on the second picture. |
|
|
546
|
Tue Oct 11 09:04:33 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
thanks for the paper. That makes
sense. I thought about sth. like that but |
|
|
584
|
Sat Jan 28 14:11:58 2017 |
Danny Petschke | AND trigger problems | Dear Stefan,
I have 2 identical pulses as a
splittet signal with an amplitude of 300mV. |
|
|
774
|
Mon Oct 14 09:32:33 2019 |
Danyang | how to acquire the stop position with channel cascading | Hi Steffan,
In DSR4
DATASHEET Rev.0.9 Page13, there is |
|
|
776
|
Mon Oct 14 11:45:06 2019 |
Danyang | how to acquire the stop position with channel cascading | I tried the
logic in my designed board. The results
are shown in the picture: Srout keeps low |
|
|
778
|
Mon Oct 14 13:44:26 2019 |
Danyang | how to acquire the stop position with channel cascading | Yes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b， A3-A0 |
|
|
780
|
Tue Oct 15 08:14:17 2019 |
Danyang | how to acquire the stop position with channel cascading | Thanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.
Best Regards, |
|
|
724
|
Thu Nov 8 11:44:35 2018 |
Davide Depaoli | Timing Issue | Hi,
We are using the DRS4 Evaluation Board as |
|
|
726
|
Thu Nov 8 12:02:34 2018 |
Davide Depaoli | Timing Issue | Thanks a lot for the quick response.
We will do as you suggest.
|
|