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Entry  Wed Sep 7 16:45:17 2011, Guillaume Blanchard, DRS4 and AD9222 
    Reply  Wed Sep 7 16:56:43 2011, Stefan Ritt, DRS4 and AD9222 
    Reply  Wed Sep 7 17:28:25 2011, Hannes Friederich, DRS4 and AD9222 
       Reply  Fri Sep 9 09:28:57 2011, Guillaume Blanchard, DRS4 and AD9222 
          Reply  Fri Sep 9 09:31:33 2011, Stefan Ritt, DRS4 and AD9222 
Message ID: 125     Entry time: Wed Sep 7 16:45:17 2011     Reply to this: 126   127
Author: Guillaume Blanchard 
Subject: DRS4 and AD9222 

Hello,

I am designing a DAQ board with both DRS4 + AD9222 and a  FPGA to monitor.

Do I have to change the default value of O-OFS ?

Does a simple low-pass filter (series resistor + capacitor) on each AD9222 input is enough to limit the noise ?

I am planning to use the (DRS4,AD9222,FPGA) group as both a trigger and digitizing system (as shown in the DRS4 datasheet). The DRS4 will be working at 5Ghz with 8 active channels.
So each channel will have a time depth of 1/5Ghz x 1024 = 204.8ns. So, in order to miss nothing, the ADC latency + the trigger decision must be inferior to 204.8ns, am I correct ?
This leads me to implement on my board the 65Mhz version of the AD9222 as this converter has a 8 clock period latency, i.e. 123ns and it left me 81ns to perform a trigger decision ?

Cordially,

G.Blanchard

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