DRS4 Forum
  DRS4 Discussion Forum, Page 1 of 12  Not logged in ELOG logo
Entry  Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue 
    Reply  Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue 
       Reply  Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue 
Entry  Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs? pi_att.PNG
    Reply  Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs? 
Entry  Sun Sep 23 02:22:46 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
       Reply  Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
          Reply  Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
Entry  Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed with.pngScreen_Shot_2018-05-17_at_13.30.23_.pngwithout.png
    Reply  Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed 
       Reply  Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed 
          Reply  Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed 
Entry  Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed eval51_adc_50ns.png
    Reply  Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed 
Entry  Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support 
    Reply  Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support 
Entry  Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing 
    Reply  Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing 
Entry  Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width bin_width_5gsps.jpgtest5gsps.dat
    Reply  Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width 
Entry  Tue Jun 19 06:42:23 2018, Phan Van Chuan, The data acquisition speed wavech0.png
    Reply  Tue Jun 19 10:05:50 2018, Stefan Ritt, The data acquisition speed 
    Reply  Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed 
Entry  Wed Jun 13 13:23:17 2018, Julian Kemp, Maximum analog input voltage 
    Reply  Wed Jun 13 13:42:47 2018, Stefan Ritt, Maximum analog input voltage 
       Reply  Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage 
Entry  Thu Jun 7 16:27:21 2018, Phan Van Chuan,  figure1.pngfigure2.png
    Reply  Fri Jun 8 08:11:05 2018, Stefan Ritt,  
Entry  Tue Feb 27 13:17:00 2018, Steven Block, WIndows Connection problem with drs507 SOLVED 
    Reply  Tue Feb 27 13:29:47 2018, Stefan Ritt, WIndows Connection problem with drs507 SOLVED 
       Reply  Wed May 9 14:07:10 2018, Alec Shackleford, WIndows Connection problem with drs507 SOLVED 
          Reply  Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED 
Entry  Tue May 8 23:58:35 2018, Sean Quinn, Manual Rev5.1 Figure 1, optional components 
    Reply  Wed May 9 09:03:52 2018, Stefan Ritt, Manual Rev5.1 Figure 1, optional components 
Entry  Wed May 2 10:44:17 2018, Alessio Berti, Peak at 0 mV in traces zero_peak_after_spike_removal_ch1.pngzero_peak_after_spike_removal_ch2.pngzero_peak_after_spike_removal_ch3.pngzero_peak_after_spike_removal_ch4.pngzero_peak_after_spike_removal_offset_correction_ch2.png
    Reply  Wed May 2 12:12:42 2018, Stefan Ritt, Peak at 0 mV in traces 
       Reply  Wed May 2 12:23:16 2018, Alessio Berti, Peak at 0 mV in traces zero_peak_after_spike_removal_ch2_1000_bins.png
          Reply  Fri May 4 11:35:20 2018, Stefan Ritt, Peak at 0 mV in traces Screen_Shot_2018-05-04_at_11.36.24_.png
             Reply  Tue May 8 12:15:54 2018, Alessio Berti, Peak at 0 mV in traces 20180508_drs4_drs_exam_1000_events_81_bins_linear.png20180508_drs4_drs_exam_1000_events_81_bins_log.png20180508_drs4_drs_exam_1000_events_23_bins_linear.png20180508_drs4_drs_exam_1000_events_23_bins_log.png
                Reply  Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces 
Entry  Wed Mar 14 09:13:39 2018, chen wenjun, confusion about the description in drs.cpp 20180314161201.jpg
    Reply  Fri Mar 16 14:00:06 2018, Stefan Ritt, confusion about the description in drs.cpp 
       Reply  Sun May 6 08:13:37 2018, chen wenjun, confusion about the description in drs.cpp 
          Reply  Sun May 6 11:45:09 2018, Stefan Ritt, confusion about the description in drs.cpp 
Entry  Wed Mar 7 22:49:38 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp drs_exam.cpp
    Reply  Thu Mar 8 22:54:20 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp 
       Reply  Fri May 4 12:11:57 2018, Stefan Ritt, Running drs_example.cpp 
    Reply  Mon Mar 19 15:12:02 2018, Stefan Ritt, Running drs_example.cpp 
Entry  Fri Apr 13 18:14:07 2018, Alessio Berti, Voltage and Timing Calibration in drs_exam.cpp 
    Reply  Fri May 4 11:56:08 2018, Stefan Ritt, Voltage and Timing Calibration in drs_exam.cpp 
Entry  Tue May 1 02:00:40 2018, Hyunseong Kim, DRS4 using drs_exam.cpp to save as binary files 
    Reply  Wed May 2 09:24:53 2018, Stefan Ritt, DRS4 using drs_exam.cpp to save as binary files 
Entry  Mon Apr 16 21:21:29 2018, Sobimpe Eniola, DRS4 read_binary.cpp  
    Reply  Tue Apr 17 13:28:23 2018, Stefan Ritt, DRS4 read_binary.cpp  
Entry  Thu Mar 22 14:36:01 2018, Phan Van Chuan, Read the CalibrateWaveform 
    Reply  Fri Mar 23 09:39:55 2018, Stefan Ritt, Read the CalibrateWaveform 
ELOG V3.1.4-966e3dd