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Entry  Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout 
    Reply  Mon Oct 24 10:30:15 2011, Stefan Ritt, Phase Shift for ADC Readout 
Message ID: 134     Entry time: Sun Oct 23 23:32:28 2011     Reply to this: 135
Author: Hao Huan 
Subject: Phase Shift for ADC Readout 

Dear Dr. Ritt,

    In the DRS 4 datasheet it is recommended to sample the analog output of the chip after 8~10 ns of the SRCLK edge for it to stablize and thus a phase shift between SRCLK and the ADC sampling clock is necessary. However in the latest version of the evaluation board firmware the phase-shifted clock was generated but not really used for the ADC interface. Is there any reason for that?

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