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Entry  Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller 
    Reply  Wed Dec 14 08:55:29 2011, Stefan Ritt, Synchronization Delay in the Firmware for 8051 Controller 
Message ID: 140     Entry time: Wed Dec 14 00:44:37 2011     Reply to this: 141
Author: Hao Huan 
Subject: Synchronization Delay in the Firmware for 8051 Controller 

Hi Stefan,

    I have a question regarding the DRS 4 evaluation board firmware for the 8051 controller embedded in the CY7C68013 USB chip: on the board the controller is running at 12 MHz and the FIFO interface of the USB chip is running at 30 MHz, so the number of delay cycles for synchronization as defined in fx2sdly.h should be (3*12000+5*30000-1)/(2*30000)=3, but the actual number used in drs_eval.c is (3*12000+5*48000-1)/(2*48000)=2, so there is a mismatch between the IFCLK frequency used in this calculation and the actual IFCLK frequency configured. Am I misunderstanding something or is there an explanation for that?

 

    Thanks,

Hao Huan

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