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Entry  Thu Jan 26 09:12:03 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
    Reply  Thu Jan 26 09:15:42 2012, Stefan Ritt, DRS4 Rev2.0 for analog pulse counting 
       Reply  Thu Jan 26 09:44:34 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
          Reply  Thu Jan 26 09:49:38 2012, Stefan Ritt, DRS4 Rev2.0 for analog pulse counting 
             Reply  Thu Jan 26 10:05:57 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
Message ID: 148     Entry time: Thu Jan 26 09:49:38 2012     In reply to: 147     Reply to this: 149
Author: Stefan Ritt 
Subject: DRS4 Rev2.0 for analog pulse counting 

Ravindra Raghunath Shinde wrote:

Stefan Ritt wrote:

Ravindra Raghunath Shinde wrote:

Hello,

We are using DRS4 Rev.2.0 board.

We want to measure number of pulses generated  by charge particle detector. These negative going analog pulses are very fast having rise time about 2nS.

We want keep threshold level to -20mV. We expected pulse rate to be about 100 to 200 Hz.

I need help to implement this in  current DRS board with  dead time free operation.

 

If you just want to count pulses, you do not need a DRS board. Just use a discriminator and a counter, that's much simpler. The DRS board is not dead time free. 

 Thanks for your prompt reply.

Along with pulse rate  we also want see pulse shape as well as charge measurements. That is why we are exploring this option with our existing DRS Set-up.

 

I understand that. But still the board has some dead time which is dominated by the USB data transfer speed.

There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months.

Best regards,

Stefan 

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