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Entry  Tue Dec 4 09:24:22 2012, Zhongwei Du, Question of drs4 using 
    Reply  Tue Dec 4 09:39:44 2012, Stefan Ritt, Question of drs4 using 
       Reply  Tue Dec 4 09:50:11 2012, Zhongwei Du, Question of drs4 using 
          Reply  Tue Dec 4 09:55:43 2012, Stefan Ritt, Question of drs4 using 
Message ID: 202     Entry time: Tue Dec 4 09:50:11 2012     In reply to: 201     Reply to this: 203
Author: Zhongwei Du 
Subject: Question of drs4 using 

Stefan Ritt wrote:

Zhongwei Du wrote:

When Denable and Dwrite is high , the voltage of PLLOUT is 0 V.  And  the Dtap is turn high with no delay when the Denable turns high.

After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first about 100 cells is rise or fall  and the last 900 cells is out of the range of ADC.

So how should I do for debugging the drs4 now.

The first thing to make work is to have DTAP oscillating with fsamp/2048. Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. If not, double check all supply voltages, and especially all soldering points. The QFN package is a bit hard to solder.

/Stefan 

 "Keep Denable and Dwrite low (required during power-on, see elog:10), set Dspeed to 2.5V, then rise Denable and Dwrite. You should see Dtap toggling at about 2.4 MHz. "

In this process ,  should i config any registers( WSR,WCR,CR  ) ?

ELOG V3.1.4-80633ba