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Entry  Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4 
    Reply  Tue Dec 15 14:38:09 2009, Stefan Ritt, Trigger of DRS4 
       Reply  Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4 
          Reply  Mon Dec 21 16:52:08 2009, Stefan Ritt, Trigger of DRS4 
             Reply  Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4 
                Reply  Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4 
Message ID: 23     Entry time: Mon Dec 14 10:14:16 2009     Reply to this: 24
Author: Jinhong Wang 
Subject: Trigger of DRS4 

Dear Mr. S. Ritt

     The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation of trigger signal to stop DRS4 sampling process for readout of sampled waveform.

     As metioned in the datasheet of DRS4, the chip samples the analog input every domino sampling period.  After finished sampling a waveform, the sampling process can be stoped by lowering the DWRITE while keeping DENABLE high. But the analog input is asychronous to the Domino CLK.  Then, how can we know when to  stop the domino sampling process to read out the sampled waveform? Of course, a trigger can be used. But from my present knowledge of DRS4, trigger can only be generated from analog input. Analog input is splited into two channels, one to DRS4 analog input, the other to FPGA as the trigger. However, splitting analog inputs increases the system design complexity, and may lower the total performace. So what is your suggestion?

    In our system, there are 8 analog inputs to a signal DRS4 chip, the outputs of DRS4 chip are connected to an 8-channel 14 bit ADC ( AD9252). It wold be kind of you to inform me about the most applicable approach for readout of DRS4 sampled wavefrom.

   Best regards.

   Sincerely,

   Jinhong Wang (wangjinh@mail.ustc.edu.cn)

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