The diagram below is DRS4 output. Green is the output8+, blue is the output8-. Output8+ of the first channel is below the baseline. It is not right.
Others channel is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code is wrong. what reason is caused? Thanks!
You are funny. Just by looking at a scope picture I should know what is wrong at your FPGA code. Unfortunately I'm not a magician. I looks to me like you have 11 channels in your diagram, although the chip has only 9. What I would recommend is to put some input to each channel one at a time, like a 10 MHz sine wave. You should then see that sine wave for the single channel at the output and can correlate input vs. output. Maybe your address bits are wrong or the chip has a soldering problem.