I want to describe this phenomenon again. The diagram below is DRS4 output. There is no input signal. Green is the output8+, blue is the output8-. Output8+ of the first channel is below the baseline. The output is saturation when input ADC. It is not right, and what is it in front of the first channel? It seemed there are two channels. Others channel is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code is wrong. What reason is caused? Can anyone help me to solve the problem? Thanks!