We're developing electronics based on the DRS4 to read out a breast PET scanner and our event rate will be quite high so we're concerned about dead-time. with that in mind, I have a question regarding the mode of simultaneous writing and reading that is described in the DRS4 data sheet. I think the description there is quite clear but I'd like to ask for a few clarifications.
1) Are the channels required to be read out via the channel multiplexer when doing the simultaneous write/read or is it ok to read out all channels in parallel (even the ones still sampling) and just throw away the ones you don't want?
2) If one wanted to use region of interest mode along with the simultaneous write/read, how would that work? Here is what I would think - please tell me if I'm missing some important detail:
-upon trigger, deassert dwrite.
-increment write config register
-start the readout (reading out stop shift register value on SROUT as data comes out)
3) now to add even more complexity - I would actually like to use simultaneous write/read along with region of interest mode and also with pairs of cascaded channels as we need >500ns latency and 2Gsps is too slow for our signals. the combination of cascading and simultaneous write/read is addressed in the data sheet but I still have one question. In normal circumstances when cascading channels, one would read out the value in the write shift register to know which channel was active when the domino wave stopped. I assume that this is not possible when dwrite is enabled as the write shift register is then advanced by the domino wave, so I see three possibilities:
-accept more dead-time and read out the write-shift-register each time (adds ~240ns to deadtime)
-just read out both channels every time and figure out later where is the data you want
-attempt to keep track of the expected state of write-shift-register in firmware.
is there a better option that I have not thought of?
Unfortunately the simultaneous writing/reading does not work as described in the data sheet. Just recently we found out that due to a bug in the chip a part of the waveform is missing if you read and write at the same time. The only clean solution is to use two DRS4 chips in parallel. You read one chip while the other samples, then you switch over between them. In that case all the ROI scheme and channel cascading works normally. The dead time will be addressed by the DRS5 chip, which will be dead time free, but will not be available until in maybe 2-3 years.