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Entry  Thu Jun 12 12:40:03 2014, Roman Gredig, DRS eval bord v5 Timing eqn1.png
    Reply  Thu Jun 12 12:46:00 2014, Stefan Ritt, DRS eval bord v5 Timing 
Message ID: 353     Entry time: Thu Jun 12 12:40:03 2014     Reply to this: 354
Author: Roman Gredig 
Subject: DRS eval bord v5 Timing 
Dear Stefan

I have two questions concerning the best time resolution with the DRS V5 eval board.
a) Calibration:
I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For all 
boards after the master I am not sure how to do it.
After setting the flag "Configure multi-board daisy-chain" in the config menu, all the slave boards set the flag "use external reference clock".  By 
hitting the voltage calibration button, the slave boards unset this flag. Is it true, that I have to re-set this before doing the time-calibration right 

b) getting the right times in binary format:
To get the time out of the time width (i.e. the t_ch[i]) you sum up in your documentation from j=0 to j=i (see attachment). In your example code 
read_binary.cpp (line 113) you sum from j=0 to j=i-1. Since you get the the bin with in the binary file, I guess that the example code is correct one?

Thank you very much,
Attachment 1: eqn1.png  8 kB  | Hide | Hide all
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