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Mon Jul 14 19:03:05 2014, Yves Bianga, change cascading from 1024 to 2048 bins for each input channel
Wed Jul 16 12:10:19 2014, Stefan Ritt, change cascading from 1024 to 2048 bins for each input channel
Mon Jul 14 19:03:05 2014
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change cascading from 1024 to 2048 bins for each input channel
I want to ask whether it is possible to modify a Evaluation Board 5.0 from 1024 to 2048 cells for each of the 4 input channels.
On the rev50 manual at page 31 I found an option to connect the 4 unused channels by setting 8 solder bridges.
The source code for controlling the board seems already prepared for 2048 bins, since version 5.0.2.
So my first question: Are there any implementations in the VHDL Code to control the write shift register in 2048 mode? / Is there a necessity for a newer/other VHDL Code or is it already implemented?
And the second: Are there any other modifications except the eight zero Ohm resistors and maybe changes in the FPGA code?
My board info output:
Mezz. Board index: 0
DRS type: DRS4
Board type: 9
Serial number: 2451
Firmware revision: 21260
Thanks a lot!