DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
Entry  Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource 
    Reply  Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource 
Message ID: 402     Entry time: Thu Apr 9 11:46:33 2015     Reply to this: 405
Author: Felix Bachmair 
Subject: DRSBoard::SetTriggerSource 

Hi

I have a question about the function SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp)

In the implementation there is the following comment:

// Set trigger configuration

// OR 0=CH1, 1=CH2, 2=CH3, 3=CH4, 4=EXT

// AND 8=CH1, 9=CH2, 10=CH3, 11=CH4, 12=EXT

 

What does this exactly mean? I am assuming that this are the bits which are set?

e.g

source = 1 ==> CH1

source = 4352 = 0x1100 ==> CH1 and ext

How is the AND/Or logic implemented?

When i have:

source = 0x1803 (bit 12,11,1,0)

what is the right way to set the brackets to expalin the logic?

(EXT and CH4 ) or CH2 or CH1 ?

 

Cheers Felix Bachmair

ETH Zurich

ELOG V3.1.4-80633ba