The problem is when you change the write config register from 11111111 to 01111111, or from 00001111 to 00000111, then the last 256 sampels of the previous channel (in the first case #0, in the scond #4) would be overwritten as soon as dwrite =1 again. So you loose 1/4 ef each channel.
Concerning the readout, indeed you can keep track in the FPGA, but only with a certainty of a few cells. This gives some timing inacccuracy of maybe 10-20 ns, which certainly would be disturbing you.
If I may trouble you for a little more information, the critical point then is that there should not be any zeroes in the write config register while the sampling is active? In case it was unclear I would only be reading out once sampling was stopped (dwrite = 0).
As for the readout, I know that I would have to read out all 1024 samples each time, and keep track of where each channel stopped in the FPGA. I would never know the exact cell where sampling stopped but I hoped that if I discard some number of cells on each side of the expected stopping point that I would be OK.
The issue with "stopping at cell 767" would also affect this mode of operation. Furthermore, the DRS4 chip has only 10 bit register which records in which cell the event has occured, and where the readout must be started. If you record 8 separate events, you don't know where to start the readout.
The DRS5 chip will have all this possibilitied, but unfortunately it won't be ready before 2-3 years from now.
I have a question about using the write config register to enable/disable sampling on the fly. I am looking to instrument an experiment at EPFL where multiple short events need to be captured during a 20us period followed by an 80us quiet period during which we could read out the chip. Would it be possible to start an acquisition with all channels seeing the same signal and the write config register set to 111111111 and then shift a zero into the write config reg after each event is detected to freeze the channels in time one-by-one? In this way we could measure up to 8 different events during the active period and then read them all out together during the quiet period. I have read the posts about the simultaneous read-write mode and the issue with waveforms stopping at cell 767. not knowing the exact details of what causes this issue I wonder if it would effect this sort of operation? Also, I would like to know if dwrite must be de-asserted while the write config register is being updated or if it could be done while the sampling is active? The latter would obviously be preferable as we would not incur any dead-time during the active period.
Thanks in advance for the information,