DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
Entry  Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting Output_Drifting.jpg
    Reply  Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting 
Message ID: 538     Entry time: Fri Sep 30 17:03:38 2016     In reply to: 537
Author: Stefan Ritt 
Subject: Output Timing Drifting 

Hi Jacob,

you are missing the timing calibration. Each sampling cell has not the same width. Running at 5 GSPS, cell widths scatter from 150 ps to 250 ps. If you integrate these widhts, you get a time scale which can be off by a few ns between chips, something you see in your plot. Here is a paper which explains in detail how to do a timing calibration: https://arxiv.org/abs/1405.4975


Jacob Hwang wrote:


I have designed four DRS4 chips (36 channels) on my board running at 1GHz (REFCLK=488.28KHz) and ROI mode. All 4 chips' REFCLK, DWRITE, RSRLOAD, and SRCLK are buffer driven by the same source.  SRCLK is set to 40MHz to reduce the readout time.

If I injected a sine waveform, buffered and splitted into all 36 channels,I noticed all 9 channels on each DRS4 chip output almost the same as expected.  But the output phase from chip to chip is drifting as shown in attached picture which is from two different channels of different chips.  From the few boards I have built, I found few chips are drifting more than the others and is different on every board.

The sympton look like the DRS4 internal PLL is drifting, but I checked the DTAP output on every chip and found it's dead-lock steady even I used persistance setting on my oscilloscope.  Do you have any suggestion how to attack this problem?  Thank you.

Jacob Hwang


ELOG V3.1.5-fc6679b