Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal routing on the DRS4 chip.
I am using a DRS4 Evaluation Board v5 and running the drsosc.exe version 5.06 on a Window 7 machine. I have performed the voltage and timing calibration.
With test pulses on channel 1 and 2, I collected binary data file with all 4 channels active sampling at 5GSPS.
Attached is a distribution of the bin_width vs. cell # for all the 4 channels. Note that there are few cells with bin_width < 10 ps.
Channel 1: bin_width = -0.000348, bin_width= -0.000348
Channel 2: bin_width = 0.007363
Channel 3: bin_width = 0.007843
Channel 4: bin_width = 0.005948
Is this normal? How can you get negative bin_width? What does negative bin_width means?
I have attached the binary data file for your verification.