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Entry  Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width bin_width_5gsps.jpgtest5gsps.dat
    Reply  Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width 
Message ID: 707     Entry time: Fri Jun 29 07:51:33 2018     In reply to: 706
Author: Stefan Ritt 
Subject: Negative Bin Width 

Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal routing on the DRS4 chip.


Woon-Seng Choong wrote:

I am using a DRS4 Evaluation Board v5 and running the drsosc.exe version 5.06 on a Window 7 machine. I have performed the voltage and timing calibration.

With test pulses on channel 1 and 2, I collected binary data file with all 4 channels active sampling at 5GSPS. 

Attached is a distribution of the bin_width vs. cell # for all the 4 channels. Note that there are few cells with bin_width < 10 ps. 

Channel 1: bin_width[498] = -0.000348, bin_width[1010]= -0.000348

Channel 2: bin_width[498] = 0.007363

Channel 3: bin_width[498] = 0.007843

Channel 4: bin_width[498] = 0.005948

Is this normal? How can you get negative bin_width? What does negative bin_width means?

I have attached the binary data file for your verification.



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