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Entry  Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study 
    Reply  Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study 
Message ID: 728     Entry time: Wed Jan 30 06:51:37 2019     Reply to this: 729
Author: Saurabh Neema 
Subject: DRS4 domino wave stability study 

We have been using DRS4 IC in our design for quite some time and it is giving good performance.

Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS by modifying the reference clock.

What I have found that DRS4 domino wave is more stable at 4 GSPS as compared to 1 GSPS by doing the timing jitter analysis. I am not sure if it is the property of DRS4 IC to be having more stable domino wave at higher frequency (by design) or it is due to some external effects like PLL loop filter or any other on board parasitic effects.

Please share if anyone has done any study of DRS4 Domino wave stability at different sampling frequencies.

Thanks,

 

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