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Entry  Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading  
    Reply  Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading  
Message ID: 834     Entry time: Sat Sep 18 15:47:50 2021     In reply to: 832
Author: Stefan Ritt 
Subject: how to acquire the stop channel with 2x4096 cascading  

The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what could be wrong:

  • Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern at WSROUT.
  • Do all tests with an oscilloscope, to avoid potential problems in your FPGA firmware (like an input configures as an output by mistake).
  • DWRITE must be high to see the contents of the WSR at the WSROUT pin, maybe that’s your mistake, see datasheet p 5 of 16.
  • To see the contents of the WSR at SROUT, A0-3 must be 1101b, please check with your oscilloscope
  • The addresses A0-A3 are simply connected to a multiplexer, so no clock is necessary after the addresses change


Jiaolong wrote:

Hi Steffan,

    I have a question about how to acquire the stop channel: 

    Process:   Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, set A3-A0 to 1101, sclk keeps 0.

    Result:   the WSROUT pin keeps 0, the SROUT pin has no clock pulse as written in datasheet, but keeps always 1 or 0. It can be seen the stop channel is channel 0 or channel 1, but no situation to represtent channel 3 or channel 4. And if set sclk with 8 pulses, the  WSROUT and SROUT both keep 0.

    What should I pay attention to? Looking forward to your reply.



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